On Sun, Mar 25, 2007 at 03:43:16AM +0200, Aurelien Jarno wrote:
Thiemo Seufer a écrit :
[...]
- Execute the second branch's delay slot instruction. Increment PC.
[...]
I'm surprised that this step would be there -- I would have expected it
to be simpler to execute the target of the first
Stuart Brady wrote:
On Sun, Mar 25, 2007 at 03:43:16AM +0200, Aurelien Jarno wrote:
Thiemo Seufer a écrit :
[...]
- Execute the second branch's delay slot instruction. Increment PC.
[...]
I'm surprised that this step would be there -- I would have expected it
to be simpler to execute
Stefan Weil wrote:
Hi,
here is the patch which adds a 4KEcR1 CPU (a 4KEc, processor revision 2.2,
with MIPS32 Release 1 (!) instruction set is the heart of the AR7 SoC).
See also include/asm-mips/cpu.h in the Linux kernel sources:
./include/asm-mips/cpu.h:#define PRID_IMP_4KEC
Thiemo Seufer a écrit :
Stefan Weil wrote:
Hi,
here is the patch which adds a 4KEcR1 CPU (a 4KEc, processor revision 2.2,
with MIPS32 Release 1 (!) instruction set is the heart of the AR7 SoC).
See also include/asm-mips/cpu.h in the Linux kernel sources:
./include/asm-mips/cpu.h:#define
Thiemo Seufer [EMAIL PROTECTED] wrote:
For the AR7 case, could you
- add AR7 as a CPU type
- handle the interesting cases for AR7 only, after verifying the
cornercase behaviour of qemu and real hardware is consistent.
AFAIK, Texas Instrument AR7 isn't a CPU. It's a SoC which
combines
Alexander Voropay wrote:
Thiemo Seufer [EMAIL PROTECTED] wrote:
For the AR7 case, could you
- add AR7 as a CPU type
- handle the interesting cases for AR7 only, after verifying the
cornercase behaviour of qemu and real hardware is consistent.
AFAIK, Texas Instrument AR7 isn't a CPU.
Hi,
here is the patch which adds a 4KEcR1 CPU (a 4KEc, processor revision 2.2,
with MIPS32 Release 1 (!) instruction set is the heart of the AR7 SoC).
See also include/asm-mips/cpu.h in the Linux kernel sources:
./include/asm-mips/cpu.h:#define PRID_IMP_4KEC 0x8400
Thank you, Paul, for your explanation which clarified Thiemo's statement.
I now checked how my published test code could contribute to a DoS attack.
Current QEMU HEAD:
* The code hangs as I wrote before. This is from a user's point of view.
Hanging means, that the test process runs in an
Stefan Weil wrote:
Thank you, Paul, for your explanation which clarified Thiemo's statement.
I now checked how my published test code could contribute to a DoS attack.
Current QEMU HEAD:
* The code hangs as I wrote before. This is from a user's point of view.
Hanging means, that the
Thiemo Seufer wrote:
[snip]
Patched QEMU HEAD (see appended patch file):
* The code works in a well defined way. An optional message in the log file
will show the faulty statement. It won't amount to a DoS because it
is disabled by default.
Sorry, but I missed the well defined.
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