On 2014/7/26 1:01, Konrad Rzeszutek Wilk wrote:
On Thu, Jul 24, 2014 at 09:44:41AM +0800, Chen, Tiejun wrote:
On 2014/7/24 4:54, Konrad Rzeszutek Wilk wrote:
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which
Il 29/07/2014 08:59, Chen, Tiejun ha scritto:
(see https://lkml.org/lkml/2014/6/19/121)
gpu:drm:i915:intel_detect_pch: back to check devfn instead of check
class
type. Because Windows always use this way, so I think this point
should be
same between Linux and Windows.
Didn't we discuss
On 2014/7/29 16:32, Paolo Bonzini wrote:
Il 29/07/2014 08:59, Chen, Tiejun ha scritto:
(see https://lkml.org/lkml/2014/6/19/121)
gpu:drm:i915:intel_detect_pch: back to check devfn instead of check
class
type. Because Windows always use this way, so I think this point
should be
same between
On Thu, Jul 24, 2014 at 09:44:41AM +0800, Chen, Tiejun wrote:
On 2014/7/24 4:54, Konrad Rzeszutek Wilk wrote:
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which
ones those are?
In
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which
ones those are?
In qemu/hw/xen_pt_igd.c/igd_pci_read(), following MCH PCI config register
reads are passthrough to the host HW. Some of the registers
On 2014/7/24 4:54, Konrad Rzeszutek Wilk wrote:
On Sat, Jul 19, 2014 at 12:27:21AM +, Kay, Allen M wrote:
For the MCH PCI registers that do need to be read - can you tell us which ones
those are?
In qemu/hw/xen_pt_igd.c/igd_pci_read(), following MCH PCI config register reads
are
On Thu, Jul 17, 2014 at 05:37:12PM +, Kay, Allen M wrote:
That sounds great. Tiejun could you confirm that with windows driver guys
too?
I believe windows driver can also assume specific CPU/PCH combos. I will
discuss this with native Windows driver guys. Preferably, the same code
For the MCH PCI registers that do need to be read - can you tell us which
ones those are?
In qemu/hw/xen_pt_igd.c/igd_pci_read(), following MCH PCI config register reads
are passthrough to the host HW. Some of the registers are needed by Ironlake
GFX driver which we probably can remove. I
That sounds great. Tiejun could you confirm that with windows driver guys too?
I believe windows driver can also assume specific CPU/PCH combos. I will
discuss this with native Windows driver guys. Preferably, the same code path
can be used for both native and virtualization cases to avoid
On Thu, Jul 03, 2014 at 11:27:40PM +0300, Michael S. Tsirkin wrote:
On Thu, Jul 03, 2014 at 12:09:28PM -0700, Jesse Barnes wrote:
On Thu, 3 Jul 2014 14:26:12 -0400
Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote:
On Thu, Jul 03, 2014 at 10:32:12AM +0300, Michael S. Tsirkin wrote:
On Thu, Jul 03, 2014 at 12:09:28PM -0700, Jesse Barnes wrote:
On Thu, 3 Jul 2014 14:26:12 -0400
Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote:
On Thu, Jul 03, 2014 at 10:32:12AM +0300, Michael S. Tsirkin wrote:
On Wed, Jul 02, 2014 at 12:23:37PM -0400, Konrad Rzeszutek Wilk wrote:
On Thu, 3 Jul 2014 14:26:12 -0400
Konrad Rzeszutek Wilk konrad.w...@oracle.com wrote:
On Thu, Jul 03, 2014 at 10:32:12AM +0300, Michael S. Tsirkin wrote:
On Wed, Jul 02, 2014 at 12:23:37PM -0400, Konrad Rzeszutek Wilk wrote:
On Wed, Jul 02, 2014 at 04:50:15PM +0200, Paolo Bonzini wrote:
12 matches
Mail list logo
