On Fri, Nov 20, 2015 at 07:58:01PM +0800, Cao jin wrote:
>
>
> On 11/20/2015 07:26 PM, Michael S. Tsirkin wrote:
> >On Fri, Nov 20, 2015 at 07:04:07PM +0800, Cao jin wrote:
> >>
> >>
> >>On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
> >>>On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin
On Fri, Nov 20, 2015 at 07:04:07PM +0800, Cao jin wrote:
>
>
> On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
> >On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin wrote:
> >>1. Do param check in pci_add_capability2(), as it is a public API.
> >
> >Separate patch pls.
>
> OK
>
> >
> >>2. As
On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin wrote:
1. Do param check in pci_add_capability2(), as it is a public API.
Separate patch pls.
OK
2. As spec says, each capability must be DWORD aligned, so an optimization can
be
1. Do param check in pci_add_capability2(), as it is a public API.
2. As spec says, each capability must be DWORD aligned, so an optimization can
be done via Loop Unrolling.
Signed-off-by: Cao jin
---
hw/pci/pci.c | 12
1 file changed, 8 insertions(+),
On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin wrote:
> 1. Do param check in pci_add_capability2(), as it is a public API.
Separate patch pls.
> 2. As spec says, each capability must be DWORD aligned, so an optimization can
>be done via Loop Unrolling.
Why do we want to optimize it?
>
On 11/20/2015 07:26 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015 at 07:04:07PM +0800, Cao jin wrote:
On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015 at 06:45:01PM +0800, Cao jin wrote:
2. As spec says, each capability must be DWORD aligned, so an optimization
On 11/20/2015 09:30 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015 at 07:58:01PM +0800, Cao jin wrote:
On 11/20/2015 07:26 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015 at 07:04:07PM +0800, Cao jin wrote:
On 11/20/2015 06:45 PM, Michael S. Tsirkin wrote:
On Fri, Nov 20, 2015