Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Benjamin Herrenschmidt
On Wed, 2013-12-18 at 23:07 +0100, Alexander Graf wrote: > On 18.12.2013, at 23:04, Benjamin Herrenschmidt > wrote: > > > On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote: > >> Then I don't understand why we break when we limit the data region to > >> 4 bytes. > > > > This is old uninort

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Alexander Graf
On 18.12.2013, at 23:04, Benjamin Herrenschmidt wrote: > On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote: >> Then I don't understand why we break when we limit the data region to >> 4 bytes. > > This is old uninorth, not U3 HT right ? The latter is memory mapped. Depends, we use the s

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Benjamin Herrenschmidt
On Wed, 2013-12-18 at 22:24 +0100, Alexander Graf wrote: > Then I don't understand why we break when we limit the data region to > 4 bytes. This is old uninorth, not U3 HT right ? The latter is memory mapped. Ben.

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Alexander Graf
On 18.12.2013, at 22:04, Benjamin Herrenschmidt wrote: > On Wed, 2013-12-18 at 13:34 +0100, Alexander Graf wrote: >> Hrm. Are you 100% sure this correct? This UniNorth is a real headache. >> The closest thing to a spec for it is the U4 spec which is generations >> ahead: >> >> http://www.data

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Benjamin Herrenschmidt
On Wed, 2013-12-18 at 13:34 +0100, Alexander Graf wrote: > Hrm. Are you 100% sure this correct? This UniNorth is a real headache. > The closest thing to a spec for it is the U4 spec which is generations > ahead: > > http://www.datasheetarchive.com/dl/Datasheets-SW3/DSASW0048084.pdf > > On that

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-12-18 Thread Alexander Graf
On 08.11.2013, at 23:18, Mark Cave-Ayland wrote: > On 08/11/13 03:20, Alexander Graf wrote: > >> On 11.10.2013, at 12:53, Mark Cave-Ayland >> wrote: >> >>> OpenBIOS prior to SVN r1225 had a horrible bug when accessing PCI >>> configuration space for PPC Mac architectures - instead of writing

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-11-08 Thread Mark Cave-Ayland
On 08/11/13 03:20, Alexander Graf wrote: On 11.10.2013, at 12:53, Mark Cave-Ayland wrote: OpenBIOS prior to SVN r1225 had a horrible bug when accessing PCI configuration space for PPC Mac architectures - instead of writing the PCI configuration data value to the data register address, it woul

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-11-07 Thread Alexander Graf
On 11.10.2013, at 12:53, Mark Cave-Ayland wrote: > OpenBIOS prior to SVN r1225 had a horrible bug when accessing PCI > configuration space for PPC Mac architectures - instead of writing the PCI > configuration data value to the data register address, it would instead write > it to the data regis

Re: [Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-10-11 Thread Hervé Poussineau
Mark Cave-Ayland a écrit : OpenBIOS prior to SVN r1225 had a horrible bug when accessing PCI configuration space for PPC Mac architectures - instead of writing the PCI configuration data value to the data register address, it would instead write it to the data register address plus the PCI config

[Qemu-devel] [PATCH] PPC: fix PCI configuration space MemoryRegions for grackle/uninorth

2013-10-11 Thread Mark Cave-Ayland
OpenBIOS prior to SVN r1225 had a horrible bug when accessing PCI configuration space for PPC Mac architectures - instead of writing the PCI configuration data value to the data register address, it would instead write it to the data register address plus the PCI configuration address. For this re