Re: [Qemu-devel] [PATCH 01/19] uninorth: trivial style fixups

2018-03-06 Thread David Gibson 
On Tue, Mar 06, 2018 at 08:30:45PM +, Mark Cave-Ayland wrote:
> This makes sure we keep patchew/checkpatch happy during the remainder of this
> patchset.
> 
> Signed-off-by: Mark Cave-Ayland 

Applied, thanks.

> ---
>  hw/pci-host/uninorth.c | 29 +++--
>  1 file changed, 19 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
> index 66991da975..710818e355 100644
> --- a/hw/pci-host/uninorth.c
> +++ b/hw/pci-host/uninorth.c
> @@ -272,7 +272,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
>  UNINState *d;
>  
>  /* Uninorth AGP bus */
> -
>  dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
>  qdev_init_nofail(dev);
>  s = SYS_BUS_DEVICE(dev);
> @@ -302,16 +301,23 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
>  
>  static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -d->config[0x34] = 0x00; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer */
> +d->config[0x34] = 0x00;
>  }
>  
>  static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -//d->config[0x34] = 0x80; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer
> +d->config[0x34] = 0x80; */
> +
>  /*
>   * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
>   * memory space with base 0x8000, size 0x1000 for Apple's
> @@ -333,9 +339,12 @@ static void u3_agp_pci_host_realize(PCIDevice *d, Error 
> **errp)
>  
>  static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -d->config[0x34] = 0x00; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer */
> +d->config[0x34] = 0x00;
>  }
>  
>  static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 01/19] uninorth: trivial style fixups

2018-03-06 Thread Philippe Mathieu-Daudé 
On 03/06/2018 05:30 PM, Mark Cave-Ayland wrote:
> This makes sure we keep patchew/checkpatch happy during the remainder of this
> patchset.
> 
> Signed-off-by: Mark Cave-Ayland 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  hw/pci-host/uninorth.c | 29 +++--
>  1 file changed, 19 insertions(+), 10 deletions(-)
> 
> diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
> index 66991da975..710818e355 100644
> --- a/hw/pci-host/uninorth.c
> +++ b/hw/pci-host/uninorth.c
> @@ -272,7 +272,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
>  UNINState *d;
>  
>  /* Uninorth AGP bus */
> -
>  dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
>  qdev_init_nofail(dev);
>  s = SYS_BUS_DEVICE(dev);
> @@ -302,16 +301,23 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
>  
>  static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -d->config[0x34] = 0x00; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer */
> +d->config[0x34] = 0x00;
>  }
>  
>  static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -//d->config[0x34] = 0x80; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer
> +d->config[0x34] = 0x80; */
> +
>  /*
>   * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
>   * memory space with base 0x8000, size 0x1000 for Apple's
> @@ -333,9 +339,12 @@ static void u3_agp_pci_host_realize(PCIDevice *d, Error 
> **errp)
>  
>  static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
>  {
> -d->config[0x0C] = 0x08; // cache_line_size
> -d->config[0x0D] = 0x10; // latency_timer
> -d->config[0x34] = 0x00; // capabilities_pointer
> +/* cache_line_size */
> +d->config[0x0C] = 0x08;
> +/* latency_timer */
> +d->config[0x0D] = 0x10;
> +/* capabilities_pointer */
> +d->config[0x34] = 0x00;
>  }
>  
>  static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
>

[Qemu-devel] [PATCH 01/19] uninorth: trivial style fixups

2018-03-06 Thread Mark Cave-Ayland 
This makes sure we keep patchew/checkpatch happy during the remainder of this
patchset.

Signed-off-by: Mark Cave-Ayland 
---
 hw/pci-host/uninorth.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
index 66991da975..710818e355 100644
--- a/hw/pci-host/uninorth.c
+++ b/hw/pci-host/uninorth.c
@@ -272,7 +272,6 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 UNINState *d;
 
 /* Uninorth AGP bus */
-
 dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
 qdev_init_nofail(dev);
 s = SYS_BUS_DEVICE(dev);
@@ -302,16 +301,23 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 
 static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
 {
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-d->config[0x34] = 0x00; // capabilities_pointer
+/* cache_line_size */
+d->config[0x0C] = 0x08;
+/* latency_timer */
+d->config[0x0D] = 0x10;
+/* capabilities_pointer */
+d->config[0x34] = 0x00;
 }
 
 static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
 {
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-//d->config[0x34] = 0x80; // capabilities_pointer
+/* cache_line_size */
+d->config[0x0C] = 0x08;
+/* latency_timer */
+d->config[0x0D] = 0x10;
+/* capabilities_pointer
+d->config[0x34] = 0x80; */
+
 /*
  * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
  * memory space with base 0x8000, size 0x1000 for Apple's
@@ -333,9 +339,12 @@ static void u3_agp_pci_host_realize(PCIDevice *d, Error 
**errp)
 
 static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
 {
-d->config[0x0C] = 0x08; // cache_line_size
-d->config[0x0D] = 0x10; // latency_timer
-d->config[0x34] = 0x00; // capabilities_pointer
+/* cache_line_size */
+d->config[0x0C] = 0x08;
+/* latency_timer */
+d->config[0x0D] = 0x10;
+/* capabilities_pointer */
+d->config[0x34] = 0x00;
 }
 
 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
-- 
2.11.0