Re: [Qemu-devel] [PATCH 04/19] target/arm: Define an IDAU interface

[Richard Henderson]

On 02/20/2018 10:03 AM, Peter Maydell wrote:
> In v8M, the Implementation Defined Attribution Unit (IDAU) is
> a small piece of hardware typically implemented in the SoC
> which provides board or SoC specific security attribution
> information for each address that the CPU performs MPU/SAU
> checks on. For QEMU, we model this with a QOM interface which
> is implemented by the board or SoC object and connected to
> the CPU using a link property.
> 
> This commit defines the new interface class, adds the link
> property to the CPU object, and makes the SAU checking
> code call the IDAU interface if one is present.
> 
> Signed-off-by: Peter Maydell 
> ---
> An example of an object that implements the IDAU can be
> found in the later patch "hw/arm/iotkit: Model Arm IOT Kit".
> ---
>  target/arm/cpu.h|  3 +++
>  target/arm/idau.h   | 61 
> +
>  target/arm/cpu.c| 15 +
>  target/arm/helper.c | 28 +---
>  4 files changed, 104 insertions(+), 3 deletions(-)
>  create mode 100644 target/arm/idau.h

Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [PATCH 04/19] target/arm: Define an IDAU interface

[Peter Maydell]

In v8M, the Implementation Defined Attribution Unit (IDAU) is
a small piece of hardware typically implemented in the SoC
which provides board or SoC specific security attribution
information for each address that the CPU performs MPU/SAU
checks on. For QEMU, we model this with a QOM interface which
is implemented by the board or SoC object and connected to
the CPU using a link property.

This commit defines the new interface class, adds the link
property to the CPU object, and makes the SAU checking
code call the IDAU interface if one is present.

Signed-off-by: Peter Maydell 
---
An example of an object that implements the IDAU can be
found in the later patch "hw/arm/iotkit: Model Arm IOT Kit".
---
 target/arm/cpu.h|  3 +++
 target/arm/idau.h   | 61 +
 target/arm/cpu.c| 15 +
 target/arm/helper.c | 28 +---
 4 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 target/arm/idau.h

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index de62df091c..dc45b740c5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -685,6 +685,9 @@ struct ARMCPU {
 /* MemoryRegion to use for secure physical accesses */
 MemoryRegion *secure_memory;
 
+/* For v8M, pointer to the IDAU interface provided by board/SoC */
+Object *idau;
+
 /* 'compatible' string for this CPU for Linux device trees */
 const char *dtb_compatible;
 
diff --git a/target/arm/idau.h b/target/arm/idau.h
new file mode 100644
index 00..cac27b95fa
--- /dev/null
+++ b/target/arm/idau.h
@@ -0,0 +1,61 @@
+/*
+ * QEMU ARM CPU -- interface for the Arm v8M IDAU
+ *
+ * Copyright (c) 2018 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * 
+ *
+ * In the v8M architecture, the IDAU is a small piece of hardware
+ * typically implemented in the SoC which provides board or SoC
+ * specific security attribution information for each address that
+ * the CPU performs MPU/SAU checks on. For QEMU, we model this with a
+ * QOM interface which is implemented by the board or SoC object and
+ * connected to the CPU using a link property.
+ */
+
+#ifndef TARGET_ARM_IDAU_H
+#define TARGET_ARM_IDAU_H
+
+#include "qom/object.h"
+
+#define TYPE_IDAU_INTERFACE "idau-interface"
+#define IDAU_INTERFACE(obj) \
+INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE)
+#define IDAU_INTERFACE_CLASS(class) \
+OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE)
+#define IDAU_INTERFACE_GET_CLASS(obj) \
+OBJECT_GET_CLASS(IDAUInterfaceClass, (obj), TYPE_IDAU_INTERFACE)
+
+typedef struct IDAUInterface {
+Object parent;
+} IDAUInterface;
+
+#define IREGION_NOTVALID -1
+
+typedef struct IDAUInterfaceClass {
+InterfaceClass parent;
+
+/* Check the specified address and return the IDAU security information
+ * for it by filling in iregion, exempt, ns and nsc:
+ *  iregion: IDAU region number, or IREGION_NOTVALID if not valid
+ *  exempt: true if address is exempt from security attribution
+ *  ns: true if the address is NonSecure
+ *  nsc: true if the address is NonSecure-callable
+ */
+void (*check)(IDAUInterface *ii, uint32_t address, int *iregion,
+  bool *exempt, bool *ns, bool *nsc);
+} IDAUInterfaceClass;
+
+#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d796085be9..99d00c3ac9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -19,6 +19,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "target/arm/idau.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
 #include "cpu.h"
@@ -687,6 +688,13 @@ static void arm_cpu_post_init(Object *obj)
 }
 }
 
+if (arm_feature(>env, ARM_FEATURE_M_SECURITY)) {
+object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, >idau,
+ qdev_prop_allow_set_link_before_realize,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ _abort);
+}
+
 qdev_property_add_static(DEVICE(obj), _cpu_cfgend_property,
  _abort);
 }
@@ -1820,11 +1828,18 @@ static const TypeInfo arm_cpu_type_info = {
 .class_init = arm_cpu_class_init,
 };
 
+static const TypeInfo idau_interface_type_info = {
+.name = TYPE_IDAU_INTERFACE,
+.parent =