On Fri, Aug 10, 2018 at 9:31 PM, Richard Henderson
wrote:
> When support for FZ16 was added, we failed to include the bit
> within FPCR_MASK, which means that it could never be set.
> Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
>
> Fixes: d81ce0ef2c4
> Cc: qemu-sta...@nongnu.org (3.0.1)
> Reported-by: Laurent Desnogues
> Signed-off-by: Richard Henderson
Tested-by: Laurent Desnogues
Reviewed-by: Laurent Desnogues
Laurent
> ---
> target/arm/cpu.h| 2 +-
> target/arm/helper.c | 5 +
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 33d06f2340..0176716a70 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1279,7 +1279,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> * we store the underlying state in fpscr and just mask on read/write.
> */
> #define FPSR_MASK 0xf89f
> -#define FPCR_MASK 0x07f79f00
> +#define FPCR_MASK 0x07ff9f00
>
> #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
> #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 64ff71b722..452d5e182a 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -11351,6 +11351,11 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env,
> uint32_t val)
> int i;
> uint32_t changed;
>
> +/* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
> +if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
> +val &= ~FPCR_FZ16;
> +}
> +
> changed = env->vfp.xregs[ARM_VFP_FPSCR];
> env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8);
> env->vfp.vec_len = (val >> 16) & 7;
> --
> 2.17.1
>
