[Qemu-devel] [PATCH 10/17] lm32: uart model
This patch add support for the LatticeMico32 UART.
Signed-off-by: Michael Walle mich...@walle.cc
---
Makefile.target |1 +
hw/lm32_uart.c | 288 +++
trace-events|5 +
3 files changed, 294 insertions(+), 0 deletions(-)
create mode 100644 hw/lm32_uart.c
diff --git a/Makefile.target b/Makefile.target
index 30a69f6..91dbf88 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -251,6 +251,7 @@ obj-ppc-y += xilinx_ethlite.o
obj-lm32-y += lm32_pic.o
obj-lm32-y += lm32_juart.o
obj-lm32-y += lm32_timer.o
+obj-lm32-y += lm32_uart.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
new file mode 100644
index 000..e225087
--- /dev/null
+++ b/hw/lm32_uart.c
@@ -0,0 +1,288 @@
+/*
+ * QEMU model of the LatticeMico32 UART block.
+ *
+ * Copyright (c) 2010 Michael Walle mich...@walle.cc
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see http://www.gnu.org/licenses/.
+ *
+ *
+ * Specification available at:
+ * http://www.latticesemi.com/documents/mico32uart.pdf
+ */
+
+
+#include hw.h
+#include sysbus.h
+#include trace.h
+#include qemu-char.h
+#include qemu-error.h
+
+enum {
+R_RXTX = 0,
+R_IER,
+R_IIR,
+R_LCR,
+R_MCR,
+R_LSR,
+R_MSR,
+R_DIV,
+R_MAX
+};
+
+enum {
+IER_RBRI = (10),
+IER_THRI = (11),
+IER_RLSI = (12),
+IER_MSI = (13),
+};
+
+enum {
+IIR_STAT = (10),
+IIR_ID0 = (11),
+IIR_ID1 = (12),
+};
+
+enum {
+LCR_WLS0 = (10),
+LCR_WLS1 = (11),
+LCR_STB = (12),
+LCR_PEN = (13),
+LCR_EPS = (14),
+LCR_SP = (15),
+LCR_SB = (16),
+};
+
+enum {
+MCR_DTR = (10),
+MCR_RTS = (11),
+};
+
+enum {
+LSR_DR = (10),
+LSR_OE = (11),
+LSR_PE = (12),
+LSR_FE = (13),
+LSR_BI = (14),
+LSR_THRE = (15),
+LSR_TEMT = (16),
+};
+
+enum {
+MSR_DCTS = (10),
+MSR_DDSR = (11),
+MSR_TERI = (12),
+MSR_DDCD = (13),
+MSR_CTS = (14),
+MSR_DSR = (15),
+MSR_RI = (16),
+MSR_DCD = (17),
+};
+
+struct LM32UartState {
+SysBusDevice busdev;
+CharDriverState *chr;
+qemu_irq irq;
+
+uint32_t regs[R_MAX];
+};
+typedef struct LM32UartState LM32UartState;
+
+static void uart_update_irq(LM32UartState *s)
+{
+unsigned int irq;
+
+if ((s-regs[R_LSR] (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
+ (s-regs[R_IER] IER_RLSI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1 | IIR_ID0;
+} else if ((s-regs[R_LSR] LSR_DR) (s-regs[R_IER] IER_RBRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1;
+} else if ((s-regs[R_LSR] LSR_THRE) (s-regs[R_IER] IER_THRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID0;
+} else if ((s-regs[R_MSR] 0x0f) (s-regs[R_IER] IER_MSI)) {
+irq = 1;
+s-regs[R_IIR] = 0;
+} else {
+irq = 0;
+s-regs[R_IIR] = IIR_STAT;
+}
+
+trace_lm32_uart_irq_state(irq);
+qemu_set_irq(s-irq, irq);
+}
+
+static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+{
+LM32UartState *s = opaque;
+uint32_t r = 0;
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+r = s-regs[R_RXTX];
+s-regs[R_LSR] = ~LSR_DR;
+uart_update_irq(s);
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+r = s-regs[addr];
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+error_report(lm32_uart: read access to write only register 0x
+TARGET_FMT_plx, addr 2);
+break;
+default:
+error_report(lm32_uart: read access to unkown register 0x
+TARGET_FMT_plx, addr 2);
+break;
+}
+
+trace_lm32_uart_memory_read(addr 2, r);
+return r;
+}
+
+static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+LM32UartState *s = opaque;
+unsigned char ch = value;
+
+trace_lm32_uart_memory_write(addr, value);
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+if (s-chr) {
+qemu_chr_write(s-chr, ch, 1);
+}
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+s-regs[addr] = value;
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+
Re: [Qemu-devel] [PATCH 10/17] lm32: uart model
On Fri, Feb 11, 2011 at 1:12 AM, Michael Walle mich...@walle.cc wrote:
This patch add support for the LatticeMico32 UART.
Signed-off-by: Michael Walle mich...@walle.cc
---
Makefile.target | 1 +
hw/lm32_uart.c | 292
+++
trace-events | 5 +
3 files changed, 298 insertions(+), 0 deletions(-)
create mode 100644 hw/lm32_uart.c
diff --git a/Makefile.target b/Makefile.target
index e0f02cf..a6bc7ac 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -252,6 +252,7 @@ obj-lm32-y += lm32_pic.o
obj-lm32-y += lm32_pic_cpu.o
obj-lm32-y += lm32_juart.o
obj-lm32-y += lm32_timer.o
+obj-lm32-y += lm32_uart.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
new file mode 100644
index 000..7c9c55c
--- /dev/null
+++ b/hw/lm32_uart.c
@@ -0,0 +1,292 @@
+/*
+ * QEMU model of the LatticeMico32 UART block.
+ *
+ * Copyright (c) 2010 Michael Walle mich...@walle.cc
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
http://www.gnu.org/licenses/.
+ *
+ *
+ * Specification available at:
+ * http://www.latticesemi.com/documents/mico32uart.pdf
+ */
+
+
+#include hw.h
+#include sysbus.h
+#include trace.h
+#include qemu-char.h
+
+enum {
+ R_RXTX = 0,
+ R_IER,
+ R_IIR,
+ R_LCR,
+ R_MCR,
+ R_LSR,
+ R_MSR,
+ R_DIV,
+ R_MAX
+};
+
+enum {
+ IER_RBRI = (10),
+ IER_THRI = (11),
+ IER_RLSI = (12),
+ IER_MSI = (13),
+};
+
+enum {
+ IIR_STAT = (10),
+ IIR_ID0 = (11),
+ IIR_ID1 = (12),
+};
+
+enum {
+ LCR_WLS0 = (10),
+ LCR_WLS1 = (11),
+ LCR_STB = (12),
+ LCR_PEN = (13),
+ LCR_EPS = (14),
+ LCR_SP = (15),
+ LCR_SB = (16),
+};
+
+enum {
+ MCR_DTR = (10),
+ MCR_RTS = (11),
+};
+
+enum {
+ LSR_DR = (10),
+ LSR_OE = (11),
+ LSR_PE = (12),
+ LSR_FE = (13),
+ LSR_BI = (14),
+ LSR_THRE = (15),
+ LSR_TEMT = (16),
+};
+
+enum {
+ MSR_DCTS = (10),
+ MSR_DDSR = (11),
+ MSR_TERI = (12),
+ MSR_DDCD = (13),
+ MSR_CTS = (14),
+ MSR_DSR = (15),
+ MSR_RI = (16),
+ MSR_DCD = (17),
+};
+
+struct LM32UartState {
+ SysBusDevice busdev;
+ CharDriverState *chr;
+ qemu_irq irq;
+
+ uint32_t regs[R_MAX];
+};
+typedef struct LM32UartState LM32UartState;
+
+static void uart_update_irq(LM32UartState *s)
+{
+ unsigned int irq;
+
+ if ((s-regs[R_LSR] (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
+ (s-regs[R_IER] IER_RLSI)) {
+ irq = 1;
+ s-regs[R_IIR] = IIR_ID1 | IIR_ID0;
+ } else if ((s-regs[R_LSR] LSR_DR) (s-regs[R_IER] IER_RBRI)) {
+ irq = 1;
+ s-regs[R_IIR] = IIR_ID1;
+ } else if ((s-regs[R_LSR] LSR_THRE) (s-regs[R_IER] IER_THRI)) {
+ irq = 1;
+ s-regs[R_IIR] = IIR_ID0;
+ } else if ((s-regs[R_MSR] 0x0f) (s-regs[R_IER] IER_MSI)) {
+ irq = 1;
+ s-regs[R_IIR] = 0;
+ } else {
+ irq = 0;
+ s-regs[R_IIR] = IIR_STAT;
+ }
+
+ trace_lm32_uart_irq_state(irq);
+ qemu_set_irq(s-irq, irq);
+}
+
+static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+{
+ LM32UartState *s = opaque;
+ uint32_t r = 0;
+
+ addr = 2;
+ switch (addr) {
+ case R_RXTX:
+ r = s-regs[R_RXTX];
+ s-regs[R_LSR] = ~LSR_DR;
+ uart_update_irq(s);
+ break;
+ case R_IIR:
+ case R_LSR:
+ case R_MSR:
+ r = s-regs[addr];
+ break;
+ case R_IER:
+ case R_LCR:
+ case R_MCR:
+ case R_DIV:
+ hw_error(lm32_uart: read access to write only register 0x
+ TARGET_FMT_plx, addr 2);
Insecure, please fix other places too.
+ break;
+
+ default:
+ hw_error(lm32_uart: read access to unkown register 0x
+ TARGET_FMT_plx, addr 2);
+ break;
+ }
+
+ trace_lm32_uart_memory_read(addr 2, r);
+
+ return r;
+}
+
+static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ LM32UartState *s = opaque;
+ unsigned char ch = value;
+
+ trace_lm32_uart_memory_write(addr, value);
+
+ addr = 2;
+ switch (addr) {
+ case
[Qemu-devel] [PATCH 10/17] lm32: uart model
This patch add support for the LatticeMico32 UART.
Signed-off-by: Michael Walle mich...@walle.cc
---
Makefile.target |1 +
hw/lm32_uart.c | 292 +++
trace-events|5 +
3 files changed, 298 insertions(+), 0 deletions(-)
create mode 100644 hw/lm32_uart.c
diff --git a/Makefile.target b/Makefile.target
index e0f02cf..a6bc7ac 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -252,6 +252,7 @@ obj-lm32-y += lm32_pic.o
obj-lm32-y += lm32_pic_cpu.o
obj-lm32-y += lm32_juart.o
obj-lm32-y += lm32_timer.o
+obj-lm32-y += lm32_uart.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
new file mode 100644
index 000..7c9c55c
--- /dev/null
+++ b/hw/lm32_uart.c
@@ -0,0 +1,292 @@
+/*
+ * QEMU model of the LatticeMico32 UART block.
+ *
+ * Copyright (c) 2010 Michael Walle mich...@walle.cc
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see http://www.gnu.org/licenses/.
+ *
+ *
+ * Specification available at:
+ * http://www.latticesemi.com/documents/mico32uart.pdf
+ */
+
+
+#include hw.h
+#include sysbus.h
+#include trace.h
+#include qemu-char.h
+
+enum {
+R_RXTX = 0,
+R_IER,
+R_IIR,
+R_LCR,
+R_MCR,
+R_LSR,
+R_MSR,
+R_DIV,
+R_MAX
+};
+
+enum {
+IER_RBRI = (10),
+IER_THRI = (11),
+IER_RLSI = (12),
+IER_MSI = (13),
+};
+
+enum {
+IIR_STAT = (10),
+IIR_ID0 = (11),
+IIR_ID1 = (12),
+};
+
+enum {
+LCR_WLS0 = (10),
+LCR_WLS1 = (11),
+LCR_STB = (12),
+LCR_PEN = (13),
+LCR_EPS = (14),
+LCR_SP = (15),
+LCR_SB = (16),
+};
+
+enum {
+MCR_DTR = (10),
+MCR_RTS = (11),
+};
+
+enum {
+LSR_DR = (10),
+LSR_OE = (11),
+LSR_PE = (12),
+LSR_FE = (13),
+LSR_BI = (14),
+LSR_THRE = (15),
+LSR_TEMT = (16),
+};
+
+enum {
+MSR_DCTS = (10),
+MSR_DDSR = (11),
+MSR_TERI = (12),
+MSR_DDCD = (13),
+MSR_CTS = (14),
+MSR_DSR = (15),
+MSR_RI = (16),
+MSR_DCD = (17),
+};
+
+struct LM32UartState {
+SysBusDevice busdev;
+CharDriverState *chr;
+qemu_irq irq;
+
+uint32_t regs[R_MAX];
+};
+typedef struct LM32UartState LM32UartState;
+
+static void uart_update_irq(LM32UartState *s)
+{
+unsigned int irq;
+
+if ((s-regs[R_LSR] (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
+ (s-regs[R_IER] IER_RLSI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1 | IIR_ID0;
+} else if ((s-regs[R_LSR] LSR_DR) (s-regs[R_IER] IER_RBRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1;
+} else if ((s-regs[R_LSR] LSR_THRE) (s-regs[R_IER] IER_THRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID0;
+} else if ((s-regs[R_MSR] 0x0f) (s-regs[R_IER] IER_MSI)) {
+irq = 1;
+s-regs[R_IIR] = 0;
+} else {
+irq = 0;
+s-regs[R_IIR] = IIR_STAT;
+}
+
+trace_lm32_uart_irq_state(irq);
+qemu_set_irq(s-irq, irq);
+}
+
+static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+{
+LM32UartState *s = opaque;
+uint32_t r = 0;
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+r = s-regs[R_RXTX];
+s-regs[R_LSR] = ~LSR_DR;
+uart_update_irq(s);
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+r = s-regs[addr];
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+hw_error(lm32_uart: read access to write only register 0x
+TARGET_FMT_plx, addr 2);
+break;
+
+default:
+hw_error(lm32_uart: read access to unkown register 0x
+TARGET_FMT_plx, addr 2);
+break;
+}
+
+trace_lm32_uart_memory_read(addr 2, r);
+
+return r;
+}
+
+static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+LM32UartState *s = opaque;
+unsigned char ch = value;
+
+trace_lm32_uart_memory_write(addr, value);
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+if (s-chr) {
+qemu_chr_write(s-chr, ch, 1);
+}
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+s-regs[addr] = value;
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+hw_error(lm32_uart: write access to
[Qemu-devel] [PATCH 10/17] lm32: uart model
This patch add support for the LatticeMico32 UART.
Signed-off-by: Michael Walle mich...@walle.cc
---
Makefile.target |1 +
hw/lm32_uart.c | 292 +++
trace-events|5 +
3 files changed, 298 insertions(+), 0 deletions(-)
create mode 100644 hw/lm32_uart.c
diff --git a/Makefile.target b/Makefile.target
index 04c4214..b5f2b2e 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -252,6 +252,7 @@ obj-lm32-y += lm32_pic.o
obj-lm32-y += lm32_pic_cpu.o
obj-lm32-y += lm32_juart.o
obj-lm32-y += lm32_timer.o
+obj-lm32-y += lm32_uart.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
new file mode 100644
index 000..7c9c55c
--- /dev/null
+++ b/hw/lm32_uart.c
@@ -0,0 +1,292 @@
+/*
+ * QEMU model of the LatticeMico32 UART block.
+ *
+ * Copyright (c) 2010 Michael Walle mich...@walle.cc
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see http://www.gnu.org/licenses/.
+ *
+ *
+ * Specification available at:
+ * http://www.latticesemi.com/documents/mico32uart.pdf
+ */
+
+
+#include hw.h
+#include sysbus.h
+#include trace.h
+#include qemu-char.h
+
+enum {
+R_RXTX = 0,
+R_IER,
+R_IIR,
+R_LCR,
+R_MCR,
+R_LSR,
+R_MSR,
+R_DIV,
+R_MAX
+};
+
+enum {
+IER_RBRI = (10),
+IER_THRI = (11),
+IER_RLSI = (12),
+IER_MSI = (13),
+};
+
+enum {
+IIR_STAT = (10),
+IIR_ID0 = (11),
+IIR_ID1 = (12),
+};
+
+enum {
+LCR_WLS0 = (10),
+LCR_WLS1 = (11),
+LCR_STB = (12),
+LCR_PEN = (13),
+LCR_EPS = (14),
+LCR_SP = (15),
+LCR_SB = (16),
+};
+
+enum {
+MCR_DTR = (10),
+MCR_RTS = (11),
+};
+
+enum {
+LSR_DR = (10),
+LSR_OE = (11),
+LSR_PE = (12),
+LSR_FE = (13),
+LSR_BI = (14),
+LSR_THRE = (15),
+LSR_TEMT = (16),
+};
+
+enum {
+MSR_DCTS = (10),
+MSR_DDSR = (11),
+MSR_TERI = (12),
+MSR_DDCD = (13),
+MSR_CTS = (14),
+MSR_DSR = (15),
+MSR_RI = (16),
+MSR_DCD = (17),
+};
+
+struct LM32UartState {
+SysBusDevice busdev;
+CharDriverState *chr;
+qemu_irq irq;
+
+uint32_t regs[R_MAX];
+};
+typedef struct LM32UartState LM32UartState;
+
+static void uart_update_irq(LM32UartState *s)
+{
+unsigned int irq;
+
+if ((s-regs[R_LSR] (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
+ (s-regs[R_IER] IER_RLSI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1 | IIR_ID0;
+} else if ((s-regs[R_LSR] LSR_DR) (s-regs[R_IER] IER_RBRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID1;
+} else if ((s-regs[R_LSR] LSR_THRE) (s-regs[R_IER] IER_THRI)) {
+irq = 1;
+s-regs[R_IIR] = IIR_ID0;
+} else if ((s-regs[R_MSR] 0x0f) (s-regs[R_IER] IER_MSI)) {
+irq = 1;
+s-regs[R_IIR] = 0;
+} else {
+irq = 0;
+s-regs[R_IIR] = IIR_STAT;
+}
+
+trace_lm32_uart_irq_state(irq);
+qemu_set_irq(s-irq, irq);
+}
+
+static uint32_t uart_read(void *opaque, target_phys_addr_t addr)
+{
+LM32UartState *s = opaque;
+uint32_t r = 0;
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+r = s-regs[R_RXTX];
+s-regs[R_LSR] = ~LSR_DR;
+uart_update_irq(s);
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+r = s-regs[addr];
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+hw_error(lm32_uart: read access to write only register 0x
+TARGET_FMT_plx, addr 2);
+break;
+
+default:
+hw_error(lm32_uart: read access to unkown register 0x
+TARGET_FMT_plx, addr 2);
+break;
+}
+
+trace_lm32_uart_memory_read(addr 2, r);
+
+return r;
+}
+
+static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+LM32UartState *s = opaque;
+unsigned char ch = value;
+
+trace_lm32_uart_memory_write(addr, value);
+
+addr = 2;
+switch (addr) {
+case R_RXTX:
+if (s-chr) {
+qemu_chr_write(s-chr, ch, 1);
+}
+break;
+case R_IER:
+case R_LCR:
+case R_MCR:
+case R_DIV:
+s-regs[addr] = value;
+break;
+case R_IIR:
+case R_LSR:
+case R_MSR:
+hw_error(lm32_uart: write access to
