Re: [Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions

On 09/26/2016 03:56 AM, Sagar Karandikar wrote: +uint64_t helper_fsgnj_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ +frs1 = (frs1 & ~(uint32_t)INT32_MIN) | (frs2 & (uint32_t)INT32_MIN); +return frs1; +} + +uint64_t helper_fsgnjn_s(CPURISCVState *env, uint64_t frs1, uint64_t

[Qemu-devel] [PATCH 10/18] target-riscv: Add Single Precision Floating-Point Instructions

Signed-off-by: Sagar Karandikar --- target-riscv/fpu_helper.c | 206 ++ target-riscv/helper.h | 28 +++ target-riscv/translate.c | 146 3 files changed, 380 insertions(+) diff --git