Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR

2016-03-19 Thread David Gibson 
On Wed, Mar 16, 2016 at 07:24:01AM +0100, Thomas Huth wrote:
> On 16.03.2016 02:14, David Gibson wrote:
> > On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
> >> From: Benjamin Herrenschmidt 
> >>
> >> We should implement HW breakpoint/watchpoint, qemu supports them...
> >>
> >> Signed-off-by: Benjamin Herrenschmidt 
> > 
> > Reviewed-by: David Gibson 
> > 
> > But I'm assuming 2.7, not 2.6.
> 
> Looks like this register can be set by the guest using the H_SET_MODE
> hypercall, too (search for H_SET_MODE_RESOURCE_SET_CIABR in the KVM
> kernel sources), similar to the DAWR register.
> And this patch is using KVM_REG_PPC_CIABR to link this register with the
> KVM code in the kernel ... so I think this patch should still go into
> 2.6 to make sure that the register is migrated properly.

Good point, not sure how I missed that.

> 
>  Thomas
> 
> >> ---
> >>  target-ppc/cpu.h| 1 +
> >>  target-ppc/translate_init.c | 5 +
> >>  2 files changed, 6 insertions(+)
> >>
> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> >> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> >> --- a/target-ppc/cpu.h
> >> +++ b/target-ppc/cpu.h
> >> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, 
> >> bool ifetch)
> >>  #define SPR_DAWR  (0x0B4)
> >>  #define SPR_MPPR  (0x0B8)
> >>  #define SPR_RPR   (0x0BA)
> >> +#define SPR_CIABR (0x0BB)
> >>  #define SPR_DAWRX (0x0BC)
> >>  #define SPR_HFSCR (0x0BE)
> >>  #define SPR_VRSAVE(0x100)
> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >> index cfb1bc088950..f88bdf7b3cd1 100644
> >> --- a/target-ppc/translate_init.c
> >> +++ b/target-ppc/translate_init.c
> >> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
> >>  SPR_NOACCESS, SPR_NOACCESS,
> >>  _read_generic, _write_generic,
> >>  KVM_REG_PPC_DAWRX, 0x);
> >> +spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> >> +SPR_NOACCESS, SPR_NOACCESS,
> >> +SPR_NOACCESS, SPR_NOACCESS,
> >> +_read_generic, _write_generic,
> >> +KVM_REG_PPC_CIABR, 0x);
> >>  }
> >>  
> >>  static void gen_spr_970_dbg(CPUPPCState *env)
> > 
> 
> 



-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR

2016-03-16 Thread Thomas Huth 
On 16.03.2016 02:14, David Gibson wrote:
> On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt 
>>
>> We should implement HW breakpoint/watchpoint, qemu supports them...
>>
>> Signed-off-by: Benjamin Herrenschmidt 
> 
> Reviewed-by: David Gibson 
> 
> But I'm assuming 2.7, not 2.6.

Looks like this register can be set by the guest using the H_SET_MODE
hypercall, too (search for H_SET_MODE_RESOURCE_SET_CIABR in the KVM
kernel sources), similar to the DAWR register.
And this patch is using KVM_REG_PPC_CIABR to link this register with the
KVM code in the kernel ... so I think this patch should still go into
2.6 to make sure that the register is migrated properly.

 Thomas

>> ---
>>  target-ppc/cpu.h| 1 +
>>  target-ppc/translate_init.c | 5 +
>>  2 files changed, 6 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index 5203cc6a3bfb..9e1ef10b7dc6 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, 
>> bool ifetch)
>>  #define SPR_DAWR  (0x0B4)
>>  #define SPR_MPPR  (0x0B8)
>>  #define SPR_RPR   (0x0BA)
>> +#define SPR_CIABR (0x0BB)
>>  #define SPR_DAWRX (0x0BC)
>>  #define SPR_HFSCR (0x0BE)
>>  #define SPR_VRSAVE(0x100)
>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>> index cfb1bc088950..f88bdf7b3cd1 100644
>> --- a/target-ppc/translate_init.c
>> +++ b/target-ppc/translate_init.c
>> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>>  SPR_NOACCESS, SPR_NOACCESS,
>>  _read_generic, _write_generic,
>>  KVM_REG_PPC_DAWRX, 0x);
>> +spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
>> +SPR_NOACCESS, SPR_NOACCESS,
>> +SPR_NOACCESS, SPR_NOACCESS,
>> +_read_generic, _write_generic,
>> +KVM_REG_PPC_CIABR, 0x);
>>  }
>>  
>>  static void gen_spr_970_dbg(CPUPPCState *env)
> 




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Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR

2016-03-15 Thread David Gibson 
On Mon, Mar 14, 2016 at 05:56:39PM +0100, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt 
> 
> We should implement HW breakpoint/watchpoint, qemu supports them...
> 
> Signed-off-by: Benjamin Herrenschmidt 

Reviewed-by: David Gibson 

But I'm assuming 2.7, not 2.6.

> ---
>  target-ppc/cpu.h| 1 +
>  target-ppc/translate_init.c | 5 +
>  2 files changed, 6 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool 
> ifetch)
>  #define SPR_DAWR  (0x0B4)
>  #define SPR_MPPR  (0x0B8)
>  #define SPR_RPR   (0x0BA)
> +#define SPR_CIABR (0x0BB)
>  #define SPR_DAWRX (0x0BC)
>  #define SPR_HFSCR (0x0BE)
>  #define SPR_VRSAVE(0x100)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index cfb1bc088950..f88bdf7b3cd1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_generic, _write_generic,
>  KVM_REG_PPC_DAWRX, 0x);
> +spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> +SPR_NOACCESS, SPR_NOACCESS,
> +SPR_NOACCESS, SPR_NOACCESS,
> +_read_generic, _write_generic,
> +KVM_REG_PPC_CIABR, 0x);
>  }
>  
>  static void gen_spr_970_dbg(CPUPPCState *env)

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR

2016-03-14 Thread Thomas Huth 
On 14.03.2016 17:56, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt 
> 
> We should implement HW breakpoint/watchpoint, qemu supports them...
> 
> Signed-off-by: Benjamin Herrenschmidt 
> ---
>  target-ppc/cpu.h| 1 +
>  target-ppc/translate_init.c | 5 +
>  2 files changed, 6 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 5203cc6a3bfb..9e1ef10b7dc6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool 
> ifetch)
>  #define SPR_DAWR  (0x0B4)
>  #define SPR_MPPR  (0x0B8)
>  #define SPR_RPR   (0x0BA)
> +#define SPR_CIABR (0x0BB)
>  #define SPR_DAWRX (0x0BC)
>  #define SPR_HFSCR (0x0BE)
>  #define SPR_VRSAVE(0x100)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index cfb1bc088950..f88bdf7b3cd1 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
>  SPR_NOACCESS, SPR_NOACCESS,
>  _read_generic, _write_generic,
>  KVM_REG_PPC_DAWRX, 0x);
> +spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
> +SPR_NOACCESS, SPR_NOACCESS,
> +SPR_NOACCESS, SPR_NOACCESS,
> +_read_generic, _write_generic,
> +KVM_REG_PPC_CIABR, 0x);
>  }
>  
>  static void gen_spr_970_dbg(CPUPPCState *env)
> 

Reviewed-by: Thomas Huth

[Qemu-devel] [PATCH 16/17] ppc: Add dummy CIABR SPR

2016-03-14 Thread Cédric Le Goater 
From: Benjamin Herrenschmidt 

We should implement HW breakpoint/watchpoint, qemu supports them...

Signed-off-by: Benjamin Herrenschmidt 
---
 target-ppc/cpu.h| 1 +
 target-ppc/translate_init.c | 5 +
 2 files changed, 6 insertions(+)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 5203cc6a3bfb..9e1ef10b7dc6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1400,6 +1400,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool 
ifetch)
 #define SPR_DAWR  (0x0B4)
 #define SPR_MPPR  (0x0B8)
 #define SPR_RPR   (0x0BA)
+#define SPR_CIABR (0x0BB)
 #define SPR_DAWRX (0x0BC)
 #define SPR_HFSCR (0x0BE)
 #define SPR_VRSAVE(0x100)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index cfb1bc088950..f88bdf7b3cd1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7603,6 +7603,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env)
 SPR_NOACCESS, SPR_NOACCESS,
 _read_generic, _write_generic,
 KVM_REG_PPC_DAWRX, 0x);
+spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
+SPR_NOACCESS, SPR_NOACCESS,
+SPR_NOACCESS, SPR_NOACCESS,
+_read_generic, _write_generic,
+KVM_REG_PPC_CIABR, 0x);
 }
 
 static void gen_spr_970_dbg(CPUPPCState *env)
-- 
2.1.4