Re: [Qemu-devel] [PATCH 2/2] hw/intc/arm_gic: reserved register addresses are RAZ/WI

2018-01-09 Thread Alistair Francis
On Wed, Dec 13, 2017 at 8:52 AM, Peter Maydell wrote: > The GICv2 specification says that reserved register addresses > must RAZ/WI; now that we implement external abort handling > for Arm CPUs this means we must return MEMTX_OK rather than > MEMTX_ERROR, to avoid

[Qemu-devel] [PATCH 2/2] hw/intc/arm_gic: reserved register addresses are RAZ/WI

2017-12-13 Thread Peter Maydell
The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Signed-off-by: Peter Maydell