On Thu, Aug 13, 2015 at 9:35 AM, Peter Maydell peter.mayd...@linaro.org wrote:
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.
Signed-off-by: Peter
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/arm-semi.c | 10 ++
1 file
