Re: [Qemu-devel] [PATCH 9/9] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

2018-03-15 Thread Philippe Mathieu-Daudé
On 03/13/2018 04:34 PM, Peter Maydell wrote: > The raspi3 has AArch64 CPUs, which means that our smpboot > code for keeping the secondary CPUs in a pen needs to have > a version for A64 as well as A32. Without this, the > secondary CPUs go into an infinite loop of taking undefined > instruction

[Qemu-devel] [PATCH 9/9] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs

2018-03-13 Thread Peter Maydell
The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell