Re: [Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

[Shlomo Pongratz]

Thanks,

I'll fix it and submit together with with the changes required by Peter.

Best regards,

S.P.

On Thursday, September 24, 2015, Christopher Covington 
wrote:

> On 09/24/2015 02:03 PM, Christopher Covington wrote:
> > Hi,
> >
> > On 09/17/2015 01:38 PM, Shlomo Pongratz wrote:
> >> From: Pavel Fedin >
> >>
> >> I would like to offer this, slightly improved implementation. The key
> thing is a new
> >> kernel_irqchip_type member in Machine class. Currently it it used only
> by virt machine for
> >> its internal purposes, however in future it is to be passed to KVM in
> >> kvm_irqchip_create(). The variable is defined as int in order to be
> architecture agnostic,
> >> for potential future users.
> >>
> >> Signed-off-by: Pavel Fedin >
> >> ---
> >>  hw/arm/virt.c | 72
> +--
> >>  include/hw/arm/fdt.h  |  2 ++
> >>  include/hw/arm/virt.h |  1 +
> >>  target-arm/machine.c  |  7 -
> >>  4 files changed, 73 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> >> index 4d15309..4c2ae7f 100644
> >> --- a/hw/arm/virt.c
> >> +++ b/hw/arm/virt.c
> >
> >> @@ -445,6 +462,14 @@ static void create_gic(VirtBoardInfo *vbi,
> qemu_irq *pic, int type, bool secure)
> >>  sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
> >>  }
> >>
> >> +if (type == 3) {
> >> +/* Connect GIC to CPU */
> >> +for (i = 0; i < smp_cpus; i++) {
> >> +CPUState *cpu = qemu_get_cpu(i);
> >> +aatch64_registers_with_opaque_set(OBJECT(cpu), (void
> *)gicdev);
> >
> > Typo--should be "aarch64".
> >
> > With that, feel free to add the following if it's any use:
> >
> > Tested-by: Christopher Covington >
>
> I originally tested building only for aarch64-softmmu, but I've now
> noticed a
> build issue with arm-softmmu.
>
> Christopher Covington
>
> --
> Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

Re: [Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

[Christopher Covington]

On 09/24/2015 02:03 PM, Christopher Covington wrote:
> Hi,
> 
> On 09/17/2015 01:38 PM, Shlomo Pongratz wrote:
>> From: Pavel Fedin 
>>
>> I would like to offer this, slightly improved implementation. The key thing 
>> is a new
>> kernel_irqchip_type member in Machine class. Currently it it used only by 
>> virt machine for
>> its internal purposes, however in future it is to be passed to KVM in
>> kvm_irqchip_create(). The variable is defined as int in order to be 
>> architecture agnostic,
>> for potential future users.
>>
>> Signed-off-by: Pavel Fedin 
>> ---
>>  hw/arm/virt.c | 72 
>> +--
>>  include/hw/arm/fdt.h  |  2 ++
>>  include/hw/arm/virt.h |  1 +
>>  target-arm/machine.c  |  7 -
>>  4 files changed, 73 insertions(+), 9 deletions(-)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index 4d15309..4c2ae7f 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
> 
>> @@ -445,6 +462,14 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq 
>> *pic, int type, bool secure)
>>  sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
>>  }
>>  
>> +if (type == 3) {
>> +/* Connect GIC to CPU */
>> +for (i = 0; i < smp_cpus; i++) {
>> +CPUState *cpu = qemu_get_cpu(i);
>> +aatch64_registers_with_opaque_set(OBJECT(cpu), (void *)gicdev);
> 
> Typo--should be "aarch64".
> 
> With that, feel free to add the following if it's any use:
> 
> Tested-by: Christopher Covington 

I originally tested building only for aarch64-softmmu, but I've now noticed a
build issue with arm-softmmu.

Christopher Covington

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

[Christopher Covington]

Hi,

On 09/17/2015 01:38 PM, Shlomo Pongratz wrote:
> From: Pavel Fedin 
> 
> I would like to offer this, slightly improved implementation. The key thing 
> is a new
> kernel_irqchip_type member in Machine class. Currently it it used only by 
> virt machine for
> its internal purposes, however in future it is to be passed to KVM in
> kvm_irqchip_create(). The variable is defined as int in order to be 
> architecture agnostic,
> for potential future users.
> 
> Signed-off-by: Pavel Fedin 
> ---
>  hw/arm/virt.c | 72 
> +--
>  include/hw/arm/fdt.h  |  2 ++
>  include/hw/arm/virt.h |  1 +
>  target-arm/machine.c  |  7 -
>  4 files changed, 73 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 4d15309..4c2ae7f 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c

> @@ -445,6 +462,14 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq 
> *pic, int type, bool secure)
>  sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
>  }
>  
> +if (type == 3) {
> +/* Connect GIC to CPU */
> +for (i = 0; i < smp_cpus; i++) {
> +CPUState *cpu = qemu_get_cpu(i);
> +aatch64_registers_with_opaque_set(OBJECT(cpu), (void *)gicdev);

Typo--should be "aarch64".

With that, feel free to add the following if it's any use:

Tested-by: Christopher Covington 

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[Qemu-devel] [PATCH RFC V4 4/4] Add virt-v3 machine that uses GIC-500

[Shlomo Pongratz]

From: Pavel Fedin 

I would like to offer this, slightly improved implementation. The key thing is 
a new
kernel_irqchip_type member in Machine class. Currently it it used only by virt 
machine for
its internal purposes, however in future it is to be passed to KVM in
kvm_irqchip_create(). The variable is defined as int in order to be 
architecture agnostic,
for potential future users.

Signed-off-by: Pavel Fedin 
---
 hw/arm/virt.c | 72 +--
 include/hw/arm/fdt.h  |  2 ++
 include/hw/arm/virt.h |  1 +
 target-arm/machine.c  |  7 -
 4 files changed, 73 insertions(+), 9 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4d15309..4c2ae7f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -71,6 +71,7 @@ typedef struct VirtBoardInfo {
 uint32_t clock_phandle;
 uint32_t gic_phandle;
 uint32_t v2m_phandle;
+const char *class_name;
 } VirtBoardInfo;
 
 typedef struct {
@@ -86,6 +87,7 @@ typedef struct {
 } VirtMachineState;
 
 #define TYPE_VIRT_MACHINE   "virt"
+#define TYPE_VIRTV3_MACHINE   "virt-v3"
 #define VIRT_MACHINE(obj) \
 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
 #define VIRT_MACHINE_GET_CLASS(obj) \
@@ -111,6 +113,7 @@ static const MemMapEntry a15memmap[] = {
 [VIRT_CPUPERIPHS] = { 0x0800, 0x0002 },
 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space 
*/
 [VIRT_GIC_DIST] =   { 0x0800, 0x0001 },
+/* Note on GICv3 VIRT_GIC_DIST_SPI takes place of VIRT_GIC_CPU */
 [VIRT_GIC_CPU] ={ 0x0801, 0x0001 },
 [VIRT_GIC_V2M] ={ 0x0802, 0x1000 },
 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
@@ -145,21 +148,26 @@ static VirtBoardInfo machines[] = {
 .cpu_model = "cortex-a15",
 .memmap = a15memmap,
 .irqmap = a15irqmap,
+.class_name = TYPE_ARM_CPU,
+
 },
 {
 .cpu_model = "cortex-a53",
 .memmap = a15memmap,
 .irqmap = a15irqmap,
+.class_name = TYPE_AARCH64_CPU,
 },
 {
 .cpu_model = "cortex-a57",
 .memmap = a15memmap,
 .irqmap = a15irqmap,
+.class_name = TYPE_AARCH64_CPU,
 },
 {
 .cpu_model = "host",
 .memmap = a15memmap,
 .irqmap = a15irqmap,
+.class_name = TYPE_ARM_CPU,
 },
 };
 
@@ -228,7 +236,6 @@ static void fdt_add_psci_node(const VirtBoardInfo *vbi)
 if (armcpu->psci_version == 2) {
 const char comp[] = "arm,psci-0.2\0arm,psci";
 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
-
 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
 if (arm_feature(>env, ARM_FEATURE_AARCH64)) {
 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
@@ -241,7 +248,6 @@ static void fdt_add_psci_node(const VirtBoardInfo *vbi)
 }
 } else {
 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
-
 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
@@ -274,6 +280,12 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi, 
int gictype)
 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
  GIC_FDT_IRQ_PPI_CPU_WIDTH,
  (1 << vbi->smp_cpus) - 1);
+} else if (gictype == 3) {
+uint32_t max;
+/* Argument is 32 bit but 8 bits are reserved for flags */
+max = (vbi->smp_cpus >= 24) ? 24 : vbi->smp_cpus;
+irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
+ GICV3_FDT_IRQ_PPI_CPU_WIDTH, (1 << max) - 1);
 }
 
 qemu_fdt_add_subnode(vbi->fdt, "/timer");
@@ -434,7 +446,12 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, 
int type, bool secure)
  */
 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
 if (!kvm_irqchip_in_kernel()) {
-qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
+if (type == 3) {
+/* AARCH64 has 4 security levels */
+qdev_prop_set_uint8(gicdev, "security-levels", secure ? 1 : 0);
+} else {
+qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
+}
 }
 qdev_init_nofail(gicdev);
 gicbusdev = SYS_BUS_DEVICE(gicdev);
@@ -445,6 +462,14 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, 
int type, bool secure)
 sysbus_mmio_map(gicbusdev, 1, vbi->memmap[VIRT_GIC_CPU].base);
 }
 
+if (type == 3) {
+/* Connect GIC to CPU */
+for (i = 0; i < smp_cpus; i++) {
+CPUState *cpu = qemu_get_cpu(i);
+aatch64_registers_with_opaque_set(OBJECT(cpu), (void *)gicdev);
+}
+}
+
 /* Wire the outputs from each CPU's generic timer to the
  * appropriate GIC PPI inputs, and the GIC's