On Mon, Jul 06, 2015 at 05:54:56PM +0200, Thomas Huth wrote:
On Mon, 6 Jul 2015 12:10:56 +1000
Alexey Kardashevskiy a...@ozlabs.ru wrote:
...
This patchset adds DDW support for pseries. The host kernel changes are
required, available in the current upstream.
This patchset is based
On Mon, Jul 06, 2015 at 12:10:56PM +1000, Alexey Kardashevskiy wrote:
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA
On Tue, 7 Jul 2015 02:07:36 +1000
Alexey Kardashevskiy a...@ozlabs.ru wrote:
On 07/07/2015 01:54 AM, Thomas Huth wrote:
On Mon, 6 Jul 2015 12:10:56 +1000
Alexey Kardashevskiy a...@ozlabs.ru wrote:
...
This patchset adds DDW support for pseries. The host kernel changes are
required,
On Mon, 6 Jul 2015 12:10:56 +1000
Alexey Kardashevskiy a...@ozlabs.ru wrote:
...
This patchset adds DDW support for pseries. The host kernel changes are
required, available in the current upstream.
This patchset is based on git://github.com/dgibson/qemu.git spapr-next branch.
Please
On 07/07/2015 01:54 AM, Thomas Huth wrote:
On Mon, 6 Jul 2015 12:10:56 +1000
Alexey Kardashevskiy a...@ozlabs.ru wrote:
...
This patchset adds DDW support for pseries. The host kernel changes are
required, available in the current upstream.
This patchset is based on
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI bus.
PAPR defines a DDW RTAS
