Re: [Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

On Fri, 22 Jun 2018 12:28:14 PDT (-0700), alistair.fran...@wdc.com wrote: Alistair Francis (5): hw/riscv/virtio: Set the soc device tree node as a simple-bus hw/riscv/virt: Increase the number of interrupts hw/riscv/virt: Connect the Xilinx PCIe hw/riscv/virt: Connect a VGA PCIe device

[Qemu-devel] [PATCH v1 0/5] Connect a PCIe host and graphics support to RISC-V

Alistair Francis (5): hw/riscv/virtio: Set the soc device tree node as a simple-bus hw/riscv/virt: Increase the number of interrupts hw/riscv/virt: Connect the Xilinx PCIe hw/riscv/virt: Connect a VGA PCIe device riscv64-softmmu.mak: Build Virtio Block support