On Wed, Mar 7, 2018 at 5:14 PM, Michael Clark wrote:
>
>
> On Wed, Mar 7, 2018 at 12:27 PM, Philippe Mathieu-Daudé
> wrote:
>
>>
>> Ok until here.
>>
>> > diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
>> > index 0aebc57..818fbdc 100644
>> > --- a/include/hw/riscv/sifive_
On Wed, Mar 7, 2018 at 12:27 PM, Philippe Mathieu-Daudé
wrote:
> Hi Michael,
>
> On 03/06/2018 05:43 PM, Michael Clark wrote:
> > Removes a whole lot of unnecessary boilerplate code. Machines
> > don't need to be objects. The expansion of the SOC object model
> > for the RISC-V machines will happ
Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unne