Re: [Qemu-devel] [PATCH v1 10/10] target/ppc: add mcrxrx instruction

[Richard Henderson]

On 02/20/2017 09:12 PM, Nikunj A Dadhania wrote:

mcrxrx: Move to CR from XER Extended

Signed-off-by: Nikunj A Dadhania 
---
 target/ppc/translate.c | 23 +++
 1 file changed, 23 insertions(+)


Reviewed-by: Richard Henderson 


r~

[Qemu-devel] [PATCH v1 10/10] target/ppc: add mcrxrx instruction

[Nikunj A Dadhania]

mcrxrx: Move to CR from XER Extended

Signed-off-by: Nikunj A Dadhania 
---
 target/ppc/translate.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ee44205..36d59a5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3816,6 +3816,28 @@ static void gen_mcrxr(DisasContext *ctx)
 tcg_gen_movi_tl(cpu_ca, 0);
 }
 
+#ifdef TARGET_PPC64
+/* mcrxrx */
+static void gen_mcrxrx(DisasContext *ctx)
+{
+TCGv t0 = tcg_temp_new();
+TCGv t1 = tcg_temp_new();
+TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
+
+/* copy OV and OV32 */
+tcg_gen_shli_tl(t0, cpu_ov, 1);
+tcg_gen_or_tl(t0, t0, cpu_ov32);
+tcg_gen_shli_tl(t0, t0, 2);
+/* copy CA and CA32 */
+tcg_gen_shli_tl(t1, cpu_ca, 1);
+tcg_gen_or_tl(t1, t1, cpu_ca32);
+tcg_gen_or_tl(t0, t0, t1);
+tcg_gen_trunc_tl_i32(dst, t0);
+tcg_temp_free(t0);
+tcg_temp_free(t1);
+}
+#endif
+
 /* mfcr mfocrf */
 static void gen_mfcr(DisasContext *ctx)
 {
@@ -6485,6 +6507,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x0801, 
PPC_MISC),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
 #endif
 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x, PPC_MISC),
-- 
2.7.4