[Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48
Signed-off-by: Michael ClarkSigned-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 -- 2.7.0
[Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48
Signed-off-by: Michael ClarkSigned-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7c4482b..f47fc9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,8 +24,8 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +#define TARGET_VIRT_ADDR_SPACE_BITS 48 #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 #define TARGET_PHYS_ADDR_SPACE_BITS 34 -- 2.7.0