Re: [Qemu-devel] [PATCH v11 16/17] hw/arm/smmuv3: IOTLB emulation

Hi Peter, On 04/17/2018 02:55 PM, Peter Maydell wrote: > On 12 April 2018 at 08:38, Eric Auger wrote: >> We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256. >> It is implemented as a hash table whose key is a combination >> of the 16b asid and 48b IOVA. >> >> Entries

Re: [Qemu-devel] [PATCH v11 16/17] hw/arm/smmuv3: IOTLB emulation

On 12 April 2018 at 08:38, Eric Auger wrote: > We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256. > It is implemented as a hash table whose key is a combination > of the 16b asid and 48b IOVA. > > Entries are invalidated on TLB invalidation commands, either > globally,

[Qemu-devel] [PATCH v11 16/17] hw/arm/smmuv3: IOTLB emulation

We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256. It is implemented as a hash table whose key is a combination of the 16b asid and 48b IOVA. Entries are invalidated on TLB invalidation commands, either globally, or per asid, or per asid/iova. One peculiarity is the NH_VA invalidation