Re: [Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

> From: Peter Maydell [mailto:peter.mayd...@linaro.org] > Sent: Tuesday, 31 October 2017 17:53 > > On 31 October 2017 at 01:23, Andrew Baumann > wrote: > >> From: Peter Maydell [mailto:peter.mayd...@linaro.org] > >> Hi. This is looking pretty good, but I have a few

Re: [Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

On 31 October 2017 at 01:23, Andrew Baumann wrote: >> From: Peter Maydell [mailto:peter.mayd...@linaro.org] >> Hi. This is looking pretty good, but I have a few comments below, >> and we're pretty much at the softfreeze date (KVM Forum last week >> meant I didn't get

Re: [Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

> From: Peter Maydell [mailto:peter.mayd...@linaro.org] > Sent: Tuesday, 31 October 2017 03:25 > > On 20 October 2017 at 22:49, Andrew Baumann > wrote: > > On a successful address translation instruction, PAR is supposed to > > contain cacheability and shareability

Re: [Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

On 20 October 2017 at 22:49, Andrew Baumann wrote: > On a successful address translation instruction, PAR is supposed to > contain cacheability and shareability attributes determined by the > translation. We previously returned 0 for these bits (in line with the >

[Qemu-devel] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers

On a successful address translation instruction, PAR is supposed to contain cacheability and shareability attributes determined by the translation. We previously returned 0 for these bits (in line with the general strategy of ignoring caches and memory attributes), but some guest OSes may depend