Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
On Tue, Jan 21, 2020 at 11:05 PM Jonathan Behrens wrote: > > I was just doubling checking the status of this patch because it conflicts > with the "RISC-V TIME CSR for privileged mode" PR that was just sent out, and > it seems this never got merged? In any case, perhaps these changes should be > rolled into that patch? I think this should be merged first. @Palmer Dabbelt can you merge this? Alistair > > On Wed, Aug 21, 2019 at 1:37 PM Palmer Dabbelt wrote: >> >> On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote: >> > Ping! What is the status of this patch? >> >> Sorry, I must have lost track of it. I've added it to my patch queue. >> >> > >> > On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens >> > wrote: >> > >> >> Bin, that proposal proved to be somewhat more controversial than I was >> >> expecting, since it was different than how currently available hardware >> >> worked. This option seemed much more likely to be accepted in the short >> >> term. >> >> >> >> Jonathan >> >> >> >> On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote: >> >> >> >>> On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis >> >>> wrote: >> >>> > >> >>> > On Mon, Jul 1, 2019 at 8:56 AM wrote: >> >>> > > >> >>> > > From: Jonathan Behrens >> >>> > > >> >>> > > QEMU currently always triggers an illegal instruction exception when >> >>> > > code attempts to read the time CSR. This is valid behavor, but only >> >>> > > if >> >>> > > the TM bit in mcounteren is hardwired to zero. This change also >> >>> > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit >> >>> > > and 64-bit targets. >> >>> > > >> >>> > > Signed-off-by: Jonathan Behrens >> >>> > >> >>> > Reviewed-by: Alistair Francis >> >>> > >> >>> >> >>> I am a little bit lost here. I think we agreed to allow directly read >> >>> to time CSR when mcounteren.TM is set, no? >> >>> >> >>> Regards, >> >>> Bin >> >>> >> >>
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
I was just doubling checking the status of this patch because it conflicts with the "RISC-V TIME CSR for privileged mode" PR that was just sent out, and it seems this never got merged? In any case, perhaps these changes should be rolled into that patch? On Wed, Aug 21, 2019 at 1:37 PM Palmer Dabbelt wrote: > On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote: > > Ping! What is the status of this patch? > > Sorry, I must have lost track of it. I've added it to my patch queue. > > > > > On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens > > wrote: > > > >> Bin, that proposal proved to be somewhat more controversial than I was > >> expecting, since it was different than how currently available hardware > >> worked. This option seemed much more likely to be accepted in the short > >> term. > >> > >> Jonathan > >> > >> On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote: > >> > >>> On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis > >>> wrote: > >>> > > >>> > On Mon, Jul 1, 2019 at 8:56 AM wrote: > >>> > > > >>> > > From: Jonathan Behrens > >>> > > > >>> > > QEMU currently always triggers an illegal instruction exception > when > >>> > > code attempts to read the time CSR. This is valid behavor, but > only if > >>> > > the TM bit in mcounteren is hardwired to zero. This change also > >>> > > corrects mcounteren and scounteren CSRs to be 32-bits on both > 32-bit > >>> > > and 64-bit targets. > >>> > > > >>> > > Signed-off-by: Jonathan Behrens > >>> > > >>> > Reviewed-by: Alistair Francis > >>> > > >>> > >>> I am a little bit lost here. I think we agreed to allow directly read > >>> to time CSR when mcounteren.TM is set, no? > >>> > >>> Regards, > >>> Bin > >>> > >> >
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
On Wed, 14 Aug 2019 20:19:39 PDT (-0700), jonat...@fintelia.io wrote: Ping! What is the status of this patch? Sorry, I must have lost track of it. I've added it to my patch queue. On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens wrote: Bin, that proposal proved to be somewhat more controversial than I was expecting, since it was different than how currently available hardware worked. This option seemed much more likely to be accepted in the short term. Jonathan On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote: On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote: > > On Mon, Jul 1, 2019 at 8:56 AM wrote: > > > > From: Jonathan Behrens > > > > QEMU currently always triggers an illegal instruction exception when > > code attempts to read the time CSR. This is valid behavor, but only if > > the TM bit in mcounteren is hardwired to zero. This change also > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit > > and 64-bit targets. > > > > Signed-off-by: Jonathan Behrens > > Reviewed-by: Alistair Francis > I am a little bit lost here. I think we agreed to allow directly read to time CSR when mcounteren.TM is set, no? Regards, Bin
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
Ping! What is the status of this patch? On Wed, Jul 3, 2019 at 2:02 PM Jonathan Behrens wrote: > Bin, that proposal proved to be somewhat more controversial than I was > expecting, since it was different than how currently available hardware > worked. This option seemed much more likely to be accepted in the short > term. > > Jonathan > > On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote: > >> On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis >> wrote: >> > >> > On Mon, Jul 1, 2019 at 8:56 AM wrote: >> > > >> > > From: Jonathan Behrens >> > > >> > > QEMU currently always triggers an illegal instruction exception when >> > > code attempts to read the time CSR. This is valid behavor, but only if >> > > the TM bit in mcounteren is hardwired to zero. This change also >> > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit >> > > and 64-bit targets. >> > > >> > > Signed-off-by: Jonathan Behrens >> > >> > Reviewed-by: Alistair Francis >> > >> >> I am a little bit lost here. I think we agreed to allow directly read >> to time CSR when mcounteren.TM is set, no? >> >> Regards, >> Bin >> >
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
Bin, that proposal proved to be somewhat more controversial than I was expecting, since it was different than how currently available hardware worked. This option seemed much more likely to be accepted in the short term. Jonathan On Mon, Jul 1, 2019 at 9:26 PM Bin Meng wrote: > On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis > wrote: > > > > On Mon, Jul 1, 2019 at 8:56 AM wrote: > > > > > > From: Jonathan Behrens > > > > > > QEMU currently always triggers an illegal instruction exception when > > > code attempts to read the time CSR. This is valid behavor, but only if > > > the TM bit in mcounteren is hardwired to zero. This change also > > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit > > > and 64-bit targets. > > > > > > Signed-off-by: Jonathan Behrens > > > > Reviewed-by: Alistair Francis > > > > I am a little bit lost here. I think we agreed to allow directly read > to time CSR when mcounteren.TM is set, no? > > Regards, > Bin >
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
On Tue, Jul 2, 2019 at 8:20 AM Alistair Francis wrote: > > On Mon, Jul 1, 2019 at 8:56 AM wrote: > > > > From: Jonathan Behrens > > > > QEMU currently always triggers an illegal instruction exception when > > code attempts to read the time CSR. This is valid behavor, but only if > > the TM bit in mcounteren is hardwired to zero. This change also > > corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit > > and 64-bit targets. > > > > Signed-off-by: Jonathan Behrens > > Reviewed-by: Alistair Francis > I am a little bit lost here. I think we agreed to allow directly read to time CSR when mcounteren.TM is set, no? Regards, Bin
Re: [Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
On Mon, Jul 1, 2019 at 8:56 AM wrote:
>
> From: Jonathan Behrens
>
> QEMU currently always triggers an illegal instruction exception when
> code attempts to read the time CSR. This is valid behavor, but only if
> the TM bit in mcounteren is hardwired to zero. This change also
> corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
> and 64-bit targets.
>
> Signed-off-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/cpu_bits.h | 5 +
> target/riscv/csr.c | 2 +-
> 3 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0adb307f32..2d0cbe9c78 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -151,8 +151,8 @@ struct CPURISCVState {
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
>
> -target_ulong scounteren;
> -target_ulong mcounteren;
> +uint32_t scounteren;
> +uint32_t mcounteren;
>
> target_ulong sscratch;
> target_ulong mscratch;
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 11f971ad5d..0ea1e1caf5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -532,4 +532,9 @@
> #define SIP_STIP MIP_STIP
> #define SIP_SEIP MIP_SEIP
>
> +/* mcounteren CSR bits */
> +#define MCOUNTEREN_CY 0x1
> +#define MCOUNTEREN_TM 0x2
> +#define MCOUNTEREN_IR 0x4
> +
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e0d4586760..8425a6d2bd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -473,7 +473,7 @@ static int write_mcounteren(CPURISCVState *env, int
> csrno, target_ulong val)
> if (env->priv_ver < PRIV_VERSION_1_10_0) {
> return -1;
> }
> -env->mcounteren = val;
> +env->mcounteren = val & ~MCOUNTEREN_TM;
> return 0;
> }
>
> --
> 2.22.0
>
[Qemu-devel] [PATCH v2] target/riscv: Hardwire mcounter.TM and upper bits of [m|s]counteren
From: Jonathan Behrens
QEMU currently always triggers an illegal instruction exception when
code attempts to read the time CSR. This is valid behavor, but only if
the TM bit in mcounteren is hardwired to zero. This change also
corrects mcounteren and scounteren CSRs to be 32-bits on both 32-bit
and 64-bit targets.
Signed-off-by: Jonathan Behrens
---
target/riscv/cpu.h | 4 ++--
target/riscv/cpu_bits.h | 5 +
target/riscv/csr.c | 2 +-
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307f32..2d0cbe9c78 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -151,8 +151,8 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
-target_ulong scounteren;
-target_ulong mcounteren;
+uint32_t scounteren;
+uint32_t mcounteren;
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 11f971ad5d..0ea1e1caf5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -532,4 +532,9 @@
#define SIP_STIP MIP_STIP
#define SIP_SEIP MIP_SEIP
+/* mcounteren CSR bits */
+#define MCOUNTEREN_CY 0x1
+#define MCOUNTEREN_TM 0x2
+#define MCOUNTEREN_IR 0x4
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0d4586760..8425a6d2bd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -473,7 +473,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno,
target_ulong val)
if (env->priv_ver < PRIV_VERSION_1_10_0) {
return -1;
}
-env->mcounteren = val;
+env->mcounteren = val & ~MCOUNTEREN_TM;
return 0;
}
--
2.22.0
