Re: [Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

2018-02-08 Thread Richard Henderson
On 02/08/2018 09:31 AM, Alex Bennée wrote: > @@ -10727,40 +10727,152 @@ static void disas_simd_two_reg_misc(DisasContext > *s, uint32_t insn) > /* AdvSIMD [scalar] two register miscellaneous (FP16) > * > * 31 30 29 28 27 24 23 22 21 17 1612 11 10 95 40 > - * +---+-

[Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

2018-02-08 Thread Alex Bennée
This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 22 target/arm/helper-a64.h| 2 + target/arm/translate-a64.c | 136 + 3 files changed, 148 i