> From: Fredrik Noring
> Subject: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special R5900
> opcodes
>
> MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
> DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
> instead of the generic
On Fri, 9 Nov 2018, Aleksandar Markovic wrote:
> > > I think that the best solution that you exclude DDIV, DDIVU, DMULT, DMULTU
> > > in a separate patch - there is no document to support their inclusion.
> >
> > As Maciej noted, the 64-bit MIPS Linux psABI is indivisible, so how could
> > your
> From: Fredrik Noring
> Subject: Re: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special
> R5900 opcodes
>
> Hi Aleksandar,
>
> > Tx79 mentions the opposite: that DDIV, DDIVU, DMULT, DMULTU are not
> > included in R5900 set.
> >
> > I think that the best solution that you exclude
> From: Fredrik Noring
> Subject: Re: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special
> R5900 opcodes
>
> Hi Aleksandar,
>
> > Tx79 mentions the opposite: that DDIV, DDIVU, DMULT, DMULTU are not
> > included in R5900 set.
> >
> > I think that the best solution that you exclude
Hi Aleksandar,
> Tx79 mentions the opposite: that DDIV, DDIVU, DMULT, DMULTU are not
> included in R5900 set.
>
> I think that the best solution that you exclude DDIV, DDIVU, DMULT, DMULTU
> in a separate patch - there is no document to support their inclusion.
As Maciej noted, the 64-bit MIPS
> From: Fredrik Noring
> Subject: Re: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special
> R5900 opcodes
>
> >
> > Could you please provide a document that would justify inclusion of these
> > non-R5900 instruction in an R5900 emulation?
>
> Would you accept the TX79 manual
On Fri, 9 Nov 2018, Aleksandar Markovic wrote:
> > ... and DMULT, DMULTU, DDIV and DDIVU
> > are part of the MIPS III ISA. They are emulated in user mode to support
> > generic MIPS III programs.
>
> Pure MIPS III executables should not be a concern of the R5900
> emulation, but R5900
Hi Aleksandar,
> > The R5900 reports itself as MIPS III ...
>
> This is very unclear. What do you mean by this? How does R5900 do that? I
> can't find any trace of such intentions in R5900 docs.
In QEMU, we have previously defined the R5900 as MIPS III by
#define CPU_R5900 (CPU_MIPS3 |
> From: Fredrik Noring
> Subject: Re: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special
> R5900 opcodes
>
> Hi Aleksandar,
>
> > Fredrik, do you know by any chance if a document exists that would justify
> > inclusion of non-R5900 DMULT, DMULTU, DDIV, DDIVU in R5900 executables by
On Thu, 8 Nov 2018, Fredrik Noring wrote:
> > Fredrik, do you know by any chance if a document exists that would justify
> > inclusion of non-R5900 DMULT, DMULTU, DDIV, DDIVU in R5900 executables by
> > gcc for R5900? Is it included by cross-gcc or by native gcc, or by both?
> >
> > I think gcc
Hi Aleksandar,
> Fredrik, do you know by any chance if a document exists that would justify
> inclusion of non-R5900 DMULT, DMULTU, DDIV, DDIVU in R5900 executables by
> gcc for R5900? Is it included by cross-gcc or by native gcc, or by both?
>
> I think gcc folks must have had a good reason for
>
> From: Fredrik Noring
> Subject: [PATCH v2 4/6] target/mips: Fix decoding mechanism of special R5900
> opcodes
>
> MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
> DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
> instead of the generic
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.
Signed-off-by: Fredrik Noring
---
target/mips/translate.c | 54 ++---
1 file
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