David Gibson wrote on 06/18/2017 04:04:48
AM:
> On Fri, Jun 16, 2017 at 11:31:02AM -0500, alar...@ddci.com wrote:
> > I haven't received any feedback on this patch, ... Did it get lost?
>
> No, I've just been busy and then sick. I'll get to it eventually..
As
G 3 wrote on 06/18/2017 03:38:29 PM:
> > From: Aaron Larson
> > Date: 06/05/2017 12:22 PM
> > Subject: [PATCH v3] target-ppc: Enable open-pic timers to count
> > and generate interrupts
> >
> > Previously QEMU open-pic
On Jun 18, 2017, at 4:36 PM, alar...@ddci.com wrote:
G 3 wrote on 06/18/2017 09:45:25 AM:
From: Aaron Larson
To: ag...@suse.de, alar...@ddci.com, da...@gibson.dropbear.id.au,
qemu-devel@nongnu.org, qemu-...@nongnu.org
Date: 06/05/2017 12:22 PM
G 3 wrote on 06/18/2017 09:45:25 AM:
> >>> From: Aaron Larson
> >>> To: ag...@suse.de, alar...@ddci.com, da...@gibson.dropbear.id.au,
> >> qemu-devel@nongnu.org, qemu-...@nongnu.org
> >>> Date: 06/05/2017 12:22 PM
> >>> Subject: [PATCH v3]
On Jun 18, 2017, at 6:50 AM, qemu-devel-requ...@nongnu.org wrote:
On Fri, Jun 16, 2017 at 11:31:02AM -0500, alar...@ddci.com wrote:
Aaron Larson wrote on 06/05/2017 12:22:53 PM:
From: Aaron Larson
To: ag...@suse.de, alar...@ddci.com,
On Mon, Jun 05, 2017 at 10:22:53AM -0700, Aaron Larson wrote:
> Previously QEMU open-pic implemented the 4 open-pic timers including
> all timer registers, but the timers did not "count" or generate any
> interrupts. The patch makes the timers both count and generate
> interrupts. The timer
On Fri, Jun 16, 2017 at 11:31:02AM -0500, alar...@ddci.com wrote:
> Aaron Larson wrote on 06/05/2017 12:22:53 PM:
>
> > From: Aaron Larson
> > To: ag...@suse.de, alar...@ddci.com, da...@gibson.dropbear.id.au,
> qemu-devel@nongnu.org, qemu-...@nongnu.org
> >
Aaron Larson wrote on 06/05/2017 12:22:53 PM:
> From: Aaron Larson
> To: ag...@suse.de, alar...@ddci.com, da...@gibson.dropbear.id.au,
qemu-devel@nongnu.org, qemu-...@nongnu.org
> Date: 06/05/2017 12:22 PM
> Subject: [PATCH v3] target-ppc: Enable open-pic
Previously QEMU open-pic implemented the 4 open-pic timers including
all timer registers, but the timers did not "count" or generate any
interrupts. The patch makes the timers both count and generate
interrupts. The timer clock frequency is fixed at 25MHZ.
--
Responding to V2 patch comments.
-