Re: [Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags

2018-02-23 Thread Richard Henderson
On 02/23/2018 07:36 AM, Alex Bennée wrote: > Half-precision flush to zero behaviour is controlled by a separate > FZ16 bit in the FPCR. To handle this we pass a pointer to > fp_status_fp16 when working on half-precision operations. The value of > the presented FPCR is calculated from an amalgam of

[Qemu-devel] [PATCH v3 04/31] target/arm/cpu.h: add additional float_status flags

2018-02-23 Thread Alex Bennée
Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Bennée