MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA CPUs. Since we are building common infrastructure for SPRs intialization to share it between 970 and POWER5+/7/..., let's add missing SPRs to the 970 family. Later rework of CPU class initialization will use those for all PowerISA CPUs.
Signed-off-by: Alexey Kardashevskiy <a...@ozlabs.ru> --- target-ppc/translate_init.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 595fd3f..cdb647a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7363,6 +7363,10 @@ static void gen_spr_book3s_pmu(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + spr_register(env, SPR_POWER_MMCRA, "MMCRA", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); spr_register(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, @@ -7379,10 +7383,22 @@ static void gen_spr_book3s_pmu(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + spr_register(env, SPR_POWER_PMC5, "PMC5", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); + spr_register(env, SPR_POWER_PMC6, "PMC6", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0x00000000); spr_register(env, SPR_POWER_SIAR, "SIAR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, SPR_NOACCESS, 0x00000000); + spr_register(env, SPR_POWER_SDAR, "SDAR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, @@ -7391,6 +7407,10 @@ static void gen_spr_book3s_pmu(CPUPPCState *env) &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); + spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); spr_register(env, SPR_POWER_UPMC1, "UPMC1", &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, @@ -7407,10 +7427,22 @@ static void gen_spr_book3s_pmu(CPUPPCState *env) &spr_read_ureg, &spr_write_ureg, &spr_read_ureg, &spr_write_ureg, 0x00000000); + spr_register(env, SPR_POWER_UPMC5, "UPMC5", + &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); + spr_register(env, SPR_POWER_UPMC6, "UPMC6", + &spr_read_ureg, &spr_write_ureg, + &spr_read_ureg, &spr_write_ureg, + 0x00000000); spr_register(env, SPR_POWER_USIAR, "USIAR", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); + spr_register(env, SPR_POWER_USDAR, "USDAR", + &spr_read_ureg, SPR_NOACCESS, + &spr_read_ureg, SPR_NOACCESS, + 0x00000000); } static void gen_spr_book3s_external_control(CPUPPCState *env) -- 1.8.4.rc4