On 04/08/2017 23:47, Alexander Bezzubikov wrote:
2017-08-04 23:28 GMT+03:00 Laszlo Ersek :
On 08/04/17 20:59, Alexander Bezzubikov wrote:
2017-08-01 20:28 GMT+03:00 Alexander Bezzubikov :
2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum :
2017-08-04 23:28 GMT+03:00 Laszlo Ersek :
> On 08/04/17 20:59, Alexander Bezzubikov wrote:
>> 2017-08-01 20:28 GMT+03:00 Alexander Bezzubikov :
>>> 2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum :
On 31/07/2017 22:01, Alexander Bezzubikov
On 08/04/17 20:59, Alexander Bezzubikov wrote:
> 2017-08-01 20:28 GMT+03:00 Alexander Bezzubikov :
>> 2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum :
>>> On 31/07/2017 22:01, Alexander Bezzubikov wrote:
2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin
2017-08-01 20:28 GMT+03:00 Alexander Bezzubikov :
> 2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum :
>> On 31/07/2017 22:01, Alexander Bezzubikov wrote:
>>>
>>> 2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin :
On Mon, Jul 31, 2017 at
2017-08-01 16:38 GMT+03:00 Marcel Apfelbaum :
> On 31/07/2017 22:01, Alexander Bezzubikov wrote:
>>
>> 2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin :
>>>
>>> On Mon, Jul 31, 2017 at 09:54:55PM +0300, Alexander Bezzubikov wrote:
2017-07-31 17:09
On 31/07/2017 22:01, Alexander Bezzubikov wrote:
2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin :
On Mon, Jul 31, 2017 at 09:54:55PM +0300, Alexander Bezzubikov wrote:
2017-07-31 17:09 GMT+03:00 Marcel Apfelbaum :
On 31/07/2017 17:00, Michael S. Tsirkin
2017-07-31 21:57 GMT+03:00 Michael S. Tsirkin :
> On Mon, Jul 31, 2017 at 09:54:55PM +0300, Alexander Bezzubikov wrote:
>> 2017-07-31 17:09 GMT+03:00 Marcel Apfelbaum :
>> > On 31/07/2017 17:00, Michael S. Tsirkin wrote:
>> >>
>> >> On Sat, Jul 29, 2017 at
On Mon, Jul 31, 2017 at 09:54:55PM +0300, Alexander Bezzubikov wrote:
> 2017-07-31 17:09 GMT+03:00 Marcel Apfelbaum :
> > On 31/07/2017 17:00, Michael S. Tsirkin wrote:
> >>
> >> On Sat, Jul 29, 2017 at 02:34:31AM +0300, Aleksandr Bezzubikov wrote:
> >>>
> >>> On PCI init PCI
2017-07-31 17:09 GMT+03:00 Marcel Apfelbaum :
> On 31/07/2017 17:00, Michael S. Tsirkin wrote:
>>
>> On Sat, Jul 29, 2017 at 02:34:31AM +0300, Aleksandr Bezzubikov wrote:
>>>
>>> On PCI init PCI bridge devices may need some
>>> extra info about bus number to reserve, IO, memory
On 31/07/2017 17:00, Michael S. Tsirkin wrote:
On Sat, Jul 29, 2017 at 02:34:31AM +0300, Aleksandr Bezzubikov wrote:
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific
On Sat, Jul 29, 2017 at 02:34:31AM +0300, Aleksandr Bezzubikov wrote:
> On PCI init PCI bridge devices may need some
> extra info about bus number to reserve, IO, memory and
> prefetchable memory limits. QEMU can provide this
> with special vendor-specific PCI capability.
>
> This capability is
On 29/07/2017 2:34, Aleksandr Bezzubikov wrote:
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red Hat PCI bridges, i.e. QEMU cooperation.
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