Re: [Qemu-devel] [PATCH v4] ppc: Add support for 'mffsl' instruction

2019-08-17 Thread David Gibson 
On Fri, Aug 16, 2019 at 02:03:23PM -0500, Paul A. Clarke wrote:
65;5603;1c> From: "Paul A. Clarke" 
> 
> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
> This patch adds support for 'mffsl'.
> 
> 'mffsl' is identical to 'mffs', except it only returns mode, status, and 
> enable
> bits from the FPSCR.
> 
> On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction
> will execute identically to 'mffs'.
> 
> Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which
> is both bits of the FPSCR rounding mode, as defined in the ISA.
> 
> I also fixed a typo in the definition of FPSCR_FR.
> 
> Signed-off-by: Paul A. Clarke 

Applied to ppc-for-4.2, thanks.

> 
> v4:
> - nit: added some braces to resolve a checkpatch complaint.
> 
> v3:
> - Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a
>   temporary, per review from Richard Henderson.
> 
> v2:
> - I found that I copied too much of the 'mffs' implementation.
>   The 'Rc' condition code bits are not needed for 'mffsl'.  Removed.
> - I now free the (renamed) 'tmask' temporary.
> - I now bail early for older ISA to the original 'mffs' implementation.
> 
> ---
>  disas/ppc.c|  5 +
>  target/ppc/cpu.h   | 15 ++-
>  target/ppc/fpu_helper.c|  4 ++--
>  target/ppc/translate/fp-impl.inc.c | 22 ++
>  target/ppc/translate/fp-ops.inc.c  |  4 +++-
>  5 files changed, 42 insertions(+), 8 deletions(-)
> 
> diff --git a/disas/ppc.c b/disas/ppc.c
> index a545437..63e97cf 100644
> --- a/disas/ppc.c
> +++ b/disas/ppc.c
> @@ -1765,6 +1765,9 @@ extract_tbr (unsigned long insn,
>  /* An X_MASK with the RA and RB fields fixed.  */
>  #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
>  
> +/* An X form instruction with the RA field fixed.  */
> +#define XRA(op, xop, ra) (X((op), (xop)) | (((ra) << 16) & XRA_MASK))
> +
>  /* An XRARB_MASK, but with the L bit clear.  */
>  #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
>  
> @@ -4998,6 +5001,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  { "ddivq",   XRC(63,546,0), X_MASK,  POWER6, { FRT, FRA, FRB } },
>  { "ddivq.",  XRC(63,546,1), X_MASK,  POWER6, { FRT, FRA, FRB } },
>  
> +{ "mffsl",   XRA(63,583,12), XRARB_MASK, POWER9, { FRT } },
> +
>  { "mffs",XRC(63,583,0), XRARB_MASK,  COM,{ FRT } },
>  { "mffs.",   XRC(63,583,1), XRARB_MASK,  COM,{ FRT } },
>  
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index c9beba2..74e8da4 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -591,7 +591,7 @@ enum {
>  #define FPSCR_XE 3  /* Floating-point inexact exception enable   
> */
>  #define FPSCR_NI 2  /* Floating-point non-IEEE mode  
> */
>  #define FPSCR_RN11
> -#define FPSCR_RN 0  /* Floating-point rounding control   
> */
> +#define FPSCR_RN00  /* Floating-point rounding control   
> */
>  #define fpscr_fex(((env->fpscr) >> FPSCR_FEX)& 0x1)
>  #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
>  #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
> @@ -614,7 +614,7 @@ enum {
>  #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
>  #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
>  #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
> -#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
> +#define fpscr_rn (((env->fpscr) >> FPSCR_RN0)& 0x3)
>  /* Invalid operation exception summary */
>  #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  
> | \
>(1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  
> | \
> @@ -640,7 +640,7 @@ enum {
>  #define FP_VXZDZ(1ull << FPSCR_VXZDZ)
>  #define FP_VXIMZ(1ull << FPSCR_VXIMZ)
>  #define FP_VXVC (1ull << FPSCR_VXVC)
> -#define FP_FR   (1ull << FSPCR_FR)
> +#define FP_FR   (1ull << FPSCR_FR)
>  #define FP_FI   (1ull << FPSCR_FI)
>  #define FP_C(1ull << FPSCR_C)
>  #define FP_FL   (1ull << FPSCR_FL)
> @@ -648,7 +648,7 @@ enum {
>  #define FP_FE   (1ull << FPSCR_FE)
>  #define FP_FU   (1ull << FPSCR_FU)
>  #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
> -#define FP_FPRF (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
> +#define FP_FPRF (FP_C | FP_FPCC)
>  #define FP_VXSOFT   (1ull << FPSCR_VXSOFT)
>  #define FP_VXSQRT   (1ull << FPSCR_VXSQRT)
>  #define FP_VXCVI(1ull << FPSCR_VXCVI)
> @@ -659,7 +659,12 @@ enum {
>  #define FP_XE   (1ull << FPSCR_XE)
>  #define FP_NI   (1ull << FPSCR_NI)
>  #define FP_RN1  (1ull << FPSCR_RN1)
> -#define FP_RN   (1ull << FPSCR_RN)
> +#define FP_RN0  (1ull << FPSCR_RN0)
> +#define FP_RN

Re: [Qemu-devel] [PATCH v4] ppc: Add support for 'mffsl' instruction

2019-08-16 Thread no-reply 
Patchew URL: 
https://patchew.org/QEMU/1565982203-11048-1-git-send-email...@us.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Subject: [Qemu-devel] [PATCH v4] ppc: Add support for 'mffsl' instruction
Message-id: 1565982203-11048-1-git-send-email...@us.ibm.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag] patchew/1565982203-11048-1-git-send-email...@us.ibm.com -> 
patchew/1565982203-11048-1-git-send-email...@us.ibm.com
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registered for path 'roms/QemuMacDrivers'
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C

[Qemu-devel] [PATCH v4] ppc: Add support for 'mffsl' instruction

2019-08-16 Thread Paul A. Clarke 
From: "Paul A. Clarke" 

ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsl'.

'mffsl' is identical to 'mffs', except it only returns mode, status, and enable
bits from the FPSCR.

On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction
will execute identically to 'mffs'.

Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which
is both bits of the FPSCR rounding mode, as defined in the ISA.

I also fixed a typo in the definition of FPSCR_FR.

Signed-off-by: Paul A. Clarke 

v4:
- nit: added some braces to resolve a checkpatch complaint.

v3:
- Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a
  temporary, per review from Richard Henderson.

v2:
- I found that I copied too much of the 'mffs' implementation.
  The 'Rc' condition code bits are not needed for 'mffsl'.  Removed.
- I now free the (renamed) 'tmask' temporary.
- I now bail early for older ISA to the original 'mffs' implementation.

---
 disas/ppc.c|  5 +
 target/ppc/cpu.h   | 15 ++-
 target/ppc/fpu_helper.c|  4 ++--
 target/ppc/translate/fp-impl.inc.c | 22 ++
 target/ppc/translate/fp-ops.inc.c  |  4 +++-
 5 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/disas/ppc.c b/disas/ppc.c
index a545437..63e97cf 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -1765,6 +1765,9 @@ extract_tbr (unsigned long insn,
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
+/* An X form instruction with the RA field fixed.  */
+#define XRA(op, xop, ra) (X((op), (xop)) | (((ra) << 16) & XRA_MASK))
+
 /* An XRARB_MASK, but with the L bit clear.  */
 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
 
@@ -4998,6 +5001,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "ddivq",   XRC(63,546,0), X_MASK,POWER6, { FRT, FRA, FRB } },
 { "ddivq.",  XRC(63,546,1), X_MASK,POWER6, { FRT, FRA, FRB } },
 
+{ "mffsl",   XRA(63,583,12), XRARB_MASK,   POWER9, { FRT } },
+
 { "mffs",XRC(63,583,0), XRARB_MASK,COM,{ FRT } },
 { "mffs.",   XRC(63,583,1), XRARB_MASK,COM,{ FRT } },
 
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c9beba2..74e8da4 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -591,7 +591,7 @@ enum {
 #define FPSCR_XE 3  /* Floating-point inexact exception enable   */
 #define FPSCR_NI 2  /* Floating-point non-IEEE mode  */
 #define FPSCR_RN11
-#define FPSCR_RN 0  /* Floating-point rounding control   */
+#define FPSCR_RN00  /* Floating-point rounding control   */
 #define fpscr_fex(((env->fpscr) >> FPSCR_FEX)& 0x1)
 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
@@ -614,7 +614,7 @@ enum {
 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
-#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
+#define fpscr_rn (((env->fpscr) >> FPSCR_RN0)& 0x3)
 /* Invalid operation exception summary */
 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
@@ -640,7 +640,7 @@ enum {
 #define FP_VXZDZ(1ull << FPSCR_VXZDZ)
 #define FP_VXIMZ(1ull << FPSCR_VXIMZ)
 #define FP_VXVC (1ull << FPSCR_VXVC)
-#define FP_FR   (1ull << FSPCR_FR)
+#define FP_FR   (1ull << FPSCR_FR)
 #define FP_FI   (1ull << FPSCR_FI)
 #define FP_C(1ull << FPSCR_C)
 #define FP_FL   (1ull << FPSCR_FL)
@@ -648,7 +648,7 @@ enum {
 #define FP_FE   (1ull << FPSCR_FE)
 #define FP_FU   (1ull << FPSCR_FU)
 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
-#define FP_FPRF (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
+#define FP_FPRF (FP_C | FP_FPCC)
 #define FP_VXSOFT   (1ull << FPSCR_VXSOFT)
 #define FP_VXSQRT   (1ull << FPSCR_VXSQRT)
 #define FP_VXCVI(1ull << FPSCR_VXCVI)
@@ -659,7 +659,12 @@ enum {
 #define FP_XE   (1ull << FPSCR_XE)
 #define FP_NI   (1ull << FPSCR_NI)
 #define FP_RN1  (1ull << FPSCR_RN1)
-#define FP_RN   (1ull << FPSCR_RN)
+#define FP_RN0  (1ull << FPSCR_RN0)
+#define FP_RN   (FP_RN1 | FP_RN0)
+
+#define FP_MODE FP_RN
+#define FP_ENABLES  (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
+#define FP_STATUS   (FP_FR | FP_FI | FP_FPRF)
 
 /* the exception bits which can be cleared by mcrfs - includes FX */
 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
diff --git