Patchew URL:
https://patchew.org/QEMU/20190904193059.26202-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190904193059.26202-1-richard.hender...@linaro.org
Type: series
Subject: [Qemu-devel] [PATCH v4 00/69] target/arm: Convert aa32 base isa to
decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
f240e8f target/arm: Inline gen_bx_im into callers
10d4d3d target/arm: Clean up disas_thumb_insn
e36cea5 target/arm: Convert T16, long branches
1061d1b target/arm: Convert T16, Unconditional branch
7c2aede target/arm: Convert T16, load (literal)
fd73031 target/arm: Convert T16, shift immediate
ac59480 target/arm: Convert T16, Miscellaneous 16-bit instructions
d0ec6df target/arm: Convert T16, Conditional branches, Supervisor call
5c1ac2f target/arm: Convert T16, push and pop
bdac1b8 target/arm: Split gen_nop_hint
0b3fed7 target/arm: Convert T16, nop hints
5021591 target/arm: Convert T16, Reverse bytes
3ec6264 target/arm: Convert T16, Change processor state
8bfb8e3 target/arm: Convert T16, extract
75466c7 target/arm: Convert T16 adjust sp (immediate)
9ab6de5 target/arm: Convert T16 add, compare, move (two high registers)
f004a7c target/arm: Convert T16 branch and exchange
cc1634d target/arm: Convert T16 one low register and immediate
d92915a target/arm: Convert T16 add/sub (3 low, 2 low and imm)
1acf8f6 target/arm: Convert T16 load/store multiple
af56e9a target/arm: Convert T16 add pc/sp (immediate)
c0275cf target/arm: Convert T16 load/store (immediate offset)
bfba5bf target/arm: Convert T16 load/store (register offset)
2f6c9ca target/arm: Convert T16 data-processing (two low regs)
994e0b4 target/arm: Add skeleton for T16 decodetree
25c88a8 target/arm: Simplify disas_arm_insn
446ed56 target/arm: Simplify disas_thumb2_insn
ee41906 target/arm: Convert TT
eb5f39d target/arm: Convert SG
39e761d target/arm: Convert Table Branch
86eec33 target/arm: Convert Unallocated memory hint
d17b1df target/arm: Convert PLI, PLD, PLDW
cdab118 target/arm: Convert SETEND
b374ec7 target/arm: Convert CPS (privileged)
fcf2c5a target/arm: Convert Clear-Exclusive, Barriers
6084bd7 target/arm: Convert RFE and SRS
d3a1d7b target/arm: Convert SVC
967a9fd target/arm: Convert B, BL, BLX (immediate)
e2925d5 target/arm: Diagnose base == pc for LDM/STM
80fca3c target/arm: Diagnose too few registers in list for LDM/STM
b585071 target/arm: Diagnose writeback register in list for LDM for v7
0d41010 target/arm: Convert LDM, STM
0318d42 target/arm: Convert MOVW, MOVT
f911da0 target/arm: Convert Signed multiply, signed and unsigned divide
dc67f09 target/arm: Convert packing, unpacking, saturation, and reversal
76b3d60 target/arm: Convert Parallel addition and subtraction
90d3a3b target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
5dbd48c target/arm: Diagnose UNPREDICTABLE ldrex/strex cases
3007337 target/arm: Convert Synchronization primitives
e27fda5 target/arm: Convert load/store (register, immediate, literal)
7f75e0f target/arm: Convert T32 ADDW/SUBW
3da4ded target/arm: Convert the rest of A32 Miscelaneous instructions
fd3df88 target/arm: Convert ERET
2116b98 target/arm: Convert CLZ
43f780c target/arm: Convert BX, BXJ, BLX (register)
e46bd40 target/arm: Convert Cyclic Redundancy Check
9824eaa target/arm: Convert MRS/MSR (banked, register)
7c864c7 target/arm: Convert MSR (immediate) and hints
f9b0422 target/arm: Simplify op_smlawx for SMLAW*
60dff02 target/arm: Simplify op_smlaxxx for SMLAL*
7de1dd4 target/arm: Convert Halfword multiply and multiply accumulate
620dfcd target/arm: Convert Saturating addition and subtraction
d795a84 target/arm: Simplify UMAAL
6d5e8d6 target/arm: Convert multiply and multiply accumulate
ed27304 target/arm: Convert Data Processing (immediate)
6b7986e target/arm: Convert Data Processing (reg-shifted-reg)
08c75f2 target/arm: Convert Data Processing (register)
92b92a6 target/arm: Add stubs for aa32 decodetree
010e06b target/arm: Use store_reg_from_load in thumb2 code
=== OUTPUT BEGIN ===
1/69 Checking commit 010e06b2e758 (target/arm: Use store_reg_from_load in
thumb2 code)
2/69 Checking commit 92b92a62ad69 (target/arm: Add stubs for aa32 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 154 lines checked
Patch 2/69 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/69 Checking commit 08c75f210ec5 (target/arm: Convert Data Processing
(register))
4/69 Checking commit 6b7986e01dc9 (target/arm: Convert Data Processing
(reg-shifted-
