Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-28 Thread David Gibson
On Wed, Nov 28, 2018 at 12:30:45PM +0100, Cédric Le Goater wrote: > On 11/28/18 1:13 AM, David Gibson wrote: > > On Fri, Nov 16, 2018 at 11:57:02AM +0100, Cédric Le Goater wrote: > >> After the event data was pushed in the O/S Event Queue, the IVPE > >> raises the bit corresponding to the priority

Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-28 Thread Cédric Le Goater
On 11/28/18 1:13 AM, David Gibson wrote: > On Fri, Nov 16, 2018 at 11:57:02AM +0100, Cédric Le Goater wrote: >> After the event data was pushed in the O/S Event Queue, the IVPE >> raises the bit corresponding to the priority of the pending interrupt >> in the register IBP (Interrupt Pending

Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-27 Thread Eric Blake
On 11/27/18 8:41 PM, David Gibson wrote: On Wed, Nov 28, 2018 at 01:32:21PM +1100, Benjamin Herrenschmidt wrote: On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote: Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size? Shouldn't be a problem as long as it fits in an

Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-27 Thread David Gibson
On Wed, Nov 28, 2018 at 01:32:21PM +1100, Benjamin Herrenschmidt wrote: > On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote: > > Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size? > > Shouldn't be a problem as long as it fits in an int, no ? I dunno, I can never

Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-27 Thread Benjamin Herrenschmidt
On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote: > Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size? Shouldn't be a problem as long as it fits in an int, no ? Cheers, Ben.

Re: [Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-27 Thread David Gibson
On Fri, Nov 16, 2018 at 11:57:02AM +0100, Cédric Le Goater wrote: > After the event data was pushed in the O/S Event Queue, the IVPE > raises the bit corresponding to the priority of the pending interrupt > in the register IBP (Interrupt Pending Buffer) to indicate there is an > event pending in

[Qemu-devel] [PATCH v5 09/36] ppc/xive: notify the CPU when the interrupt priority is more privileged

2018-11-16 Thread Cédric Le Goater
After the event data was pushed in the O/S Event Queue, the IVPE raises the bit corresponding to the priority of the pending interrupt in the register IBP (Interrupt Pending Buffer) to indicate there is an event pending in one of the 8 priority queues. The Pending Interrupt Priority Register