Re: [Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext

[Philippe Mathieu-Daudé]

On 03/01/2018 07:53 PM, Emilio G. Cota wrote:
> No changes to the logic here; this is just to make the diff
> that follows easier to read.
> 
> While at it, remove the unnecessary 'struct' in
> 'struct TranslationBlock'.
> 
> Note that checkpatch complains with a false positive:
>   ERROR: space prohibited after that '&' (ctx:WxW)
>   #75: FILE: target/mips/translate.c:20220:
>   +ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
>   ^
> Cc: Aurelien Jarno 
> Cc: Yongbok Kim 
> Signed-off-by: Emilio G. Cota 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  target/mips/translate.c | 166 
> 
>  1 file changed, 84 insertions(+), 82 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index aefd729..08bd140 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, 
> DisasContext *ctx)
>  }
>  }
>  
> -void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
>  {
>  CPUMIPSState *env = cs->env_ptr;
> -DisasContext ctx;
> +DisasContext ctx1;
> +DisasContext *ctx = 
>  target_ulong next_page_start;
>  int max_insns;
>  int insn_bytes;
>  int is_slot;
>  
> -ctx.base.tb = tb;
> -ctx.base.pc_first = tb->pc;
> -ctx.base.pc_next = tb->pc;
> -ctx.base.is_jmp = DISAS_NEXT;
> -ctx.base.singlestep_enabled = cs->singlestep_enabled;
> -ctx.base.num_insns = 0;
> -
> -next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + 
> TARGET_PAGE_SIZE;
> -ctx.saved_pc = -1;
> -ctx.insn_flags = env->insn_flags;
> -ctx.CP0_Config1 = env->CP0_Config1;
> -ctx.btarget = 0;
> -ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> -ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> -ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
> -ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
> -ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
> -ctx.PAMask = env->PAMask;
> -ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
> -ctx.eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
> -ctx.sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
> -ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
> -ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
> +ctx->base.tb = tb;
> +ctx->base.pc_first = tb->pc;
> +ctx->base.pc_next = tb->pc;
> +ctx->base.is_jmp = DISAS_NEXT;
> +ctx->base.singlestep_enabled = cs->singlestep_enabled;
> +ctx->base.num_insns = 0;
> +
> +next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
> +TARGET_PAGE_SIZE;
> +ctx->saved_pc = -1;
> +ctx->insn_flags = env->insn_flags;
> +ctx->CP0_Config1 = env->CP0_Config1;
> +ctx->btarget = 0;
> +ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
> +ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
> +ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
> +ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
> +ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
> +ctx->PAMask = env->PAMask;
> +ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
> +ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
> +ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
> +ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
> +ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
>  /* Restore delay slot state from the tb context.  */
> -ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? 
> */
> -ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> -ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
> +ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 
> bits? */
> +ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
> +ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
>   (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
> -ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
> -ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
> -ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
> -ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> -restore_cpu_state(env, );
> +ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
> +ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
> +ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
> +ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> +restore_cpu_state(env, ctx);
>  #ifdef CONFIG_USER_ONLY
> -ctx.mem_idx = MIPS_HFLAG_UM;
> +ctx->mem_idx = MIPS_HFLAG_UM;
>  #else
> -ctx.mem_idx = hflags_mmu_index(ctx.hflags);
> +ctx->mem_idx = hflags_mmu_index(ctx->hflags);
>  #endif
> -ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
> -   

[Qemu-devel] [PATCHv1 08/14] target/mips: use *ctx for DisasContext

[Emilio G. Cota]

No changes to the logic here; this is just to make the diff
that follows easier to read.

While at it, remove the unnecessary 'struct' in
'struct TranslationBlock'.

Note that checkpatch complains with a false positive:
  ERROR: space prohibited after that '&' (ctx:WxW)
  #75: FILE: target/mips/translate.c:20220:
  +ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
  ^
Cc: Aurelien Jarno 
Cc: Yongbok Kim 
Signed-off-by: Emilio G. Cota 
---
 target/mips/translate.c | 166 
 1 file changed, 84 insertions(+), 82 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index aefd729..08bd140 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20194,55 +20194,57 @@ static void decode_opc(CPUMIPSState *env, 
DisasContext *ctx)
 }
 }
 
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
 {
 CPUMIPSState *env = cs->env_ptr;
-DisasContext ctx;
+DisasContext ctx1;
+DisasContext *ctx = 
 target_ulong next_page_start;
 int max_insns;
 int insn_bytes;
 int is_slot;
 
-ctx.base.tb = tb;
-ctx.base.pc_first = tb->pc;
-ctx.base.pc_next = tb->pc;
-ctx.base.is_jmp = DISAS_NEXT;
-ctx.base.singlestep_enabled = cs->singlestep_enabled;
-ctx.base.num_insns = 0;
-
-next_page_start = (ctx.base.pc_first & TARGET_PAGE_MASK) + 
TARGET_PAGE_SIZE;
-ctx.saved_pc = -1;
-ctx.insn_flags = env->insn_flags;
-ctx.CP0_Config1 = env->CP0_Config1;
-ctx.btarget = 0;
-ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
-ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
-ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
-ctx.bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
-ctx.bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
-ctx.PAMask = env->PAMask;
-ctx.mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
-ctx.eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
-ctx.sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
-ctx.CP0_LLAddr_shift = env->CP0_LLAddr_shift;
-ctx.cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
+ctx->base.tb = tb;
+ctx->base.pc_first = tb->pc;
+ctx->base.pc_next = tb->pc;
+ctx->base.is_jmp = DISAS_NEXT;
+ctx->base.singlestep_enabled = cs->singlestep_enabled;
+ctx->base.num_insns = 0;
+
+next_page_start = (ctx->base.pc_first & TARGET_PAGE_MASK) +
+TARGET_PAGE_SIZE;
+ctx->saved_pc = -1;
+ctx->insn_flags = env->insn_flags;
+ctx->CP0_Config1 = env->CP0_Config1;
+ctx->btarget = 0;
+ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
+ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
+ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
+ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
+ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
+ctx->PAMask = env->PAMask;
+ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
+ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
+ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
+ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
+ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
 /* Restore delay slot state from the tb context.  */
-ctx.hflags = (uint32_t)ctx.base.tb->flags; /* FIXME: maybe use 64 bits? */
-ctx.ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
-ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
+ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? 
*/
+ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
+ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
  (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
-ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
-ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
-ctx.nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
-ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
-restore_cpu_state(env, );
+ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
+ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
+ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
+ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+restore_cpu_state(env, ctx);
 #ifdef CONFIG_USER_ONLY
-ctx.mem_idx = MIPS_HFLAG_UM;
+ctx->mem_idx = MIPS_HFLAG_UM;
 #else
-ctx.mem_idx = hflags_mmu_index(ctx.hflags);
+ctx->mem_idx = hflags_mmu_index(ctx->hflags);
 #endif
-ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ?
- MO_UNALN : MO_ALIGN;
+ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
+  MO_UNALN : MO_ALIGN;
 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
 if (max_insns == 0) {
 max_insns = CF_COUNT_MASK;
@@ -20251,74 +20253,74 @@ void