Hi Phil,
On Tue, 2017-08-01 at 00:23 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 07/31/2017 10:04 PM, Andrew Jeffery wrote:
> > The reset width register controls how the pulse on the SoC's WDTRST{1,2}
> > pins behaves. A pulse is emitted if the external reset bit is set in
> >
Hi Andrew,
On 07/31/2017 10:04 PM, Andrew Jeffery wrote:
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. WDT_RESET_WIDTH requires magic bit patterns to configure both
push-pull/open-drain and
