Re: [Qemu-devel] [RFC PATCH v4 64/75] target/i386: introduce AVX2 vector instructions to sse-opcode.inc.h
21.08.2019. 20.49, "Jan Bobek" је написао/ла: > > Add all the AVX2 vector instruction entries to sse-opcode.inc.h. > Why is AVX-related code inserted in a file whose name says SSE? Perhaps the file should be named vector-opcode.inc.h? Also, some vector extensions contain non-vector instructions. Even if you don't intend to implement emulation of such instructions, you should mention them in places like this file, since this file mainly deals with decoding, which is known to you. Without it, you leave the file unfinished without a good reason. Thanks, Aleksandar > Signed-off-by: Jan Bobek > --- > target/i386/sse-opcode.inc.h | 362 ++- > 1 file changed, 359 insertions(+), 3 deletions(-) > > diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h > index c3c0ec4f89..abbb0a15d7 100644 > --- a/target/i386/sse-opcode.inc.h > +++ b/target/i386/sse-opcode.inc.h > @@ -855,6 +855,181 @@ > * VEX.128.66.0F.WIG 73 /3 ib VPSRLDQ xmm1, xmm2, imm8 > * VEX.LZ.0F.WIG AE /2 VLDMXCSR m32 > * VEX.LZ.0F.WIG AE /3 VSTMXCSR m32 > + * > + * AVX2 Instructions > + * -- > + * VEX.256.66.0F.W0 D7 /r VPMOVMSKB r32, ymm1 > + * VEX.256.66.0F.W1 D7 /r VPMOVMSKB r64, ymm1 > + * VEX.256.66.0F.WIG FC /r VPADDB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG FD /r VPADDW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG FE /r VPADDD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG D4 /r VPADDQ ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG EC /r VPADDSB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG ED /r VPADDSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG DC /r VPADDUSB ymm1,ymm2,ymm3/m256 > + * VEX.256.66.0F.WIG DD /r VPADDUSW ymm1,ymm2,ymm3/m256 > + * VEX.256.66.0F38.WIG 01 /r VPHADDW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 02 /r VPHADDD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 03 /r VPHADDSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG F8 /r VPSUBB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG F9 /r VPSUBW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG FA /r VPSUBD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG FB /r VPSUBQ ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E8 /r VPSUBSB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E9 /r VPSUBSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG D8 /r VPSUBUSB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG D9 /r VPSUBUSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 05 /r VPHSUBW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 06 /r VPHSUBD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 07 /r VPHSUBSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG D5 /r VPMULLW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 40 /r VPMULLD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E5 /r VPMULHW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E4 /r VPMULHUW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 28 /r VPMULDQ ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG F4 /r VPMULUDQ ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 0B /r VPMULHRSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG F5 /r VPMADDWD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 04 /r VPMADDUBSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F DA /r VPMINUB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38 3A /r VPMINUW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 3B /r VPMINUD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38 38 /r VPMINSB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F EA /r VPMINSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 39 /r VPMINSD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F DE /r VPMAXUB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38 3E /r VPMAXUW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 3F /r VPMAXUD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 3C /r VPMAXSB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG EE /r VPMAXSW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 3D /r VPMAXSD ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E0 /r VPAVGB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG E3 /r VPAVGW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG F6 /r VPSADBW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F3A.WIG 42 /r ibVMPSADBW ymm1, ymm2, ymm3/m256, imm8 > + * VEX.256.66.0F38.WIG 1C /r VPABSB ymm1, ymm2/m256 > + * VEX.256.66.0F38.WIG 1D /r VPABSW ymm1, ymm2/m256 > + * VEX.256.66.0F38.WIG 1E /r VPABSD ymm1, ymm2/m256 > + * VEX.256.66.0F38.WIG 08 /r VPSIGNB ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 09 /r VPSIGNW ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F38.WIG 0A /r VPSIGND ymm1, ymm2, ymm3/m256 > + * VEX.256.66.0F.WIG 74 /r VPCMPEQB ymm1,ymm2,ymm3/m256 > + * VEX.256.66.0F.WIG 75 /r VPCMPEQW
[Qemu-devel] [RFC PATCH v4 64/75] target/i386: introduce AVX2 vector instructions to sse-opcode.inc.h
Add all the AVX2 vector instruction entries to sse-opcode.inc.h. Signed-off-by: Jan Bobek --- target/i386/sse-opcode.inc.h | 362 ++- 1 file changed, 359 insertions(+), 3 deletions(-) diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h index c3c0ec4f89..abbb0a15d7 100644 --- a/target/i386/sse-opcode.inc.h +++ b/target/i386/sse-opcode.inc.h @@ -855,6 +855,181 @@ * VEX.128.66.0F.WIG 73 /3 ib VPSRLDQ xmm1, xmm2, imm8 * VEX.LZ.0F.WIG AE /2 VLDMXCSR m32 * VEX.LZ.0F.WIG AE /3 VSTMXCSR m32 + * + * AVX2 Instructions + * -- + * VEX.256.66.0F.W0 D7 /r VPMOVMSKB r32, ymm1 + * VEX.256.66.0F.W1 D7 /r VPMOVMSKB r64, ymm1 + * VEX.256.66.0F.WIG FC /r VPADDB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG FD /r VPADDW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG FE /r VPADDD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG D4 /r VPADDQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG EC /r VPADDSB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG ED /r VPADDSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG DC /r VPADDUSB ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F.WIG DD /r VPADDUSW ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F38.WIG 01 /r VPHADDW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 02 /r VPHADDD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 03 /r VPHADDSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG F8 /r VPSUBB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG F9 /r VPSUBW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG FA /r VPSUBD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG FB /r VPSUBQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E8 /r VPSUBSB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E9 /r VPSUBSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG D8 /r VPSUBUSB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG D9 /r VPSUBUSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 05 /r VPHSUBW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 06 /r VPHSUBD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 07 /r VPHSUBSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG D5 /r VPMULLW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 40 /r VPMULLD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E5 /r VPMULHW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E4 /r VPMULHUW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 28 /r VPMULDQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG F4 /r VPMULUDQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 0B /r VPMULHRSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG F5 /r VPMADDWD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 04 /r VPMADDUBSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F DA /r VPMINUB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38 3A /r VPMINUW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 3B /r VPMINUD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38 38 /r VPMINSB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F EA /r VPMINSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 39 /r VPMINSD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F DE /r VPMAXUB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38 3E /r VPMAXUW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 3F /r VPMAXUD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 3C /r VPMAXSB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG EE /r VPMAXSW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 3D /r VPMAXSD ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E0 /r VPAVGB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG E3 /r VPAVGW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG F6 /r VPSADBW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F3A.WIG 42 /r ibVMPSADBW ymm1, ymm2, ymm3/m256, imm8 + * VEX.256.66.0F38.WIG 1C /r VPABSB ymm1, ymm2/m256 + * VEX.256.66.0F38.WIG 1D /r VPABSW ymm1, ymm2/m256 + * VEX.256.66.0F38.WIG 1E /r VPABSD ymm1, ymm2/m256 + * VEX.256.66.0F38.WIG 08 /r VPSIGNB ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 09 /r VPSIGNW ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F38.WIG 0A /r VPSIGND ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG 74 /r VPCMPEQB ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F.WIG 75 /r VPCMPEQW ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F.WIG 76 /r VPCMPEQD ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F38.WIG 29 /r VPCMPEQQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG 64 /r VPCMPGTB ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F.WIG 65 /r VPCMPGTW ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F.WIG 66 /r VPCMPGTD ymm1,ymm2,ymm3/m256 + * VEX.256.66.0F38.WIG 37 /r VPCMPGTQ ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG DB /r VPAND ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG DF /r VPANDN ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG EB /r VPOR ymm1, ymm2, ymm3/m256 + * VEX.256.66.0F.WIG EF /r VPXOR ymm1, ymm2,
