Yes, this is what i meant.
Am 8. Juli 2016 09:01:59 MESZ, schrieb David Kiarie :
>On Mon, Jul 4, 2016 at 8:41 AM, Jan Kiszka wrote:
>> On 2016-07-04 07:06, David Kiarie wrote:
>>> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka
>wrote:
On 2016-06-15 14:21, David Kiarie wrote:
> +
> +
On Mon, Jul 4, 2016 at 8:41 AM, Jan Kiszka wrote:
> On 2016-07-04 07:06, David Kiarie wrote:
>> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka wrote:
>>> On 2016-06-15 14:21, David Kiarie wrote:
+
+
+/* PCI SIG constants */
+#define PCI_BUS_MAX 256
+#define PCI_SLOT_MAX 32
On 2016-07-04 07:49, David Kiarie wrote:
> +/* FIXME: something might go wrong if System Software writes in chunks
> + * of one byte but linux writes in chunks of 4 bytes so currently it
> + * works correctly with linux but will definitely be busted if software
> + * reads/writes 8
On Mon, Jul 4, 2016 at 8:41 AM, Jan Kiszka wrote:
> On 2016-07-04 07:06, David Kiarie wrote:
>> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka wrote:
>>> On 2016-06-15 14:21, David Kiarie wrote:
+static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size)
+{
+AMDVIS
On 2016-07-04 07:06, David Kiarie wrote:
> On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka wrote:
>> On 2016-06-15 14:21, David Kiarie wrote:
>>> +static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size)
>>> +{
>>> +AMDVIState *s = opaque;
>>> +
>>> +uint64_t val = -1;
>>> +
On Wed, Jun 22, 2016 at 11:24 PM, Jan Kiszka wrote:
> On 2016-06-15 14:21, David Kiarie wrote:
>> +
>> +/* System Software might never read from some of this fields but anyways */
>
> No read-modify-write accesses observed in the field? And fields like
> AMDVI_MMIO_STATUS or AMDVI_MMIO_EXT_FEATURE
On 2016-06-15 14:21, David Kiarie wrote:
> Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU
> The IOMMU does basic translation, error checking and has a
> minimal IOTLB implementation. This IOMMU bypassed the need
> for target aborts by responding with IOMMU_NONE access rights
> and exempt
Add AMD IOMMU emulaton to Qemu in addition to Intel IOMMU
The IOMMU does basic translation, error checking and has a
minimal IOTLB implementation. This IOMMU bypassed the need
for target aborts by responding with IOMMU_NONE access rights
and exempts the region 0xfee0-0xfeef from translation
