Re: [Qemu-devel] [for-4.2 PATCH 2/2] hw/i386: AMD-Vi IVRS DMA alias support

2019-07-29 Thread Peter Xu
On Mon, Jul 29, 2019 at 01:04:41PM -0600, Alex Williamson wrote: > On Mon, 29 Jul 2019 16:26:46 +0800 > Peter Xu wrote: > > > On Fri, Jul 26, 2019 at 06:55:53PM -0600, Alex Williamson wrote: > > > When we account for DMA aliases in the PCI address space, we can no > > > longer use a single IVHD

Re: [Qemu-devel] [for-4.2 PATCH 2/2] hw/i386: AMD-Vi IVRS DMA alias support

2019-07-29 Thread Alex Williamson
On Mon, 29 Jul 2019 16:26:46 +0800 Peter Xu wrote: > On Fri, Jul 26, 2019 at 06:55:53PM -0600, Alex Williamson wrote: > > When we account for DMA aliases in the PCI address space, we can no > > longer use a single IVHD entry in the IVRS covering all devices. We > > instead need to walk the PCI

Re: [Qemu-devel] [for-4.2 PATCH 2/2] hw/i386: AMD-Vi IVRS DMA alias support

2019-07-29 Thread Peter Xu
On Fri, Jul 26, 2019 at 06:55:53PM -0600, Alex Williamson wrote: > When we account for DMA aliases in the PCI address space, we can no > longer use a single IVHD entry in the IVRS covering all devices. We > instead need to walk the PCI bus and create alias ranges when we find > a conventional

[Qemu-devel] [for-4.2 PATCH 2/2] hw/i386: AMD-Vi IVRS DMA alias support

2019-07-26 Thread Alex Williamson
When we account for DMA aliases in the PCI address space, we can no longer use a single IVHD entry in the IVRS covering all devices. We instead need to walk the PCI bus and create alias ranges when we find a conventional bus. These alias ranges cannot overlap with a "Select All" range (as