On 6/25/19 12:41 PM, Daniel P. Berrangé wrote:
> On Tue, Jun 25, 2019 at 12:36:35PM +0200, Philippe Mathieu-Daudé wrote:
>> On 6/25/19 1:24 AM, Alistair Francis wrote:
>>> On Mon, Jun 24, 2019 at 3:57 PM Atish Patra wrote:
Currently, there is no cpu topology defined in RISC-V.
On Tue, Jun 25, 2019 at 12:36:35PM +0200, Philippe Mathieu-Daudé wrote:
> On 6/25/19 1:24 AM, Alistair Francis wrote:
> > On Mon, Jun 24, 2019 at 3:57 PM Atish Patra wrote:
> >>
> >> Currently, there is no cpu topology defined in RISC-V.
> >> Define a device tree node that clearly describes the
>
On 6/25/19 1:24 AM, Alistair Francis wrote:
> On Mon, Jun 24, 2019 at 3:57 PM Atish Patra wrote:
>>
>> Currently, there is no cpu topology defined in RISC-V.
>> Define a device tree node that clearly describes the
>> entire topology. This saves the trouble of scanning individual
>> cache to
On Mon, 2019-06-24 at 16:24 -0700, Alistair Francis wrote:
> On Mon, Jun 24, 2019 at 3:57 PM Atish Patra
> wrote:
> > Currently, there is no cpu topology defined in RISC-V.
> > Define a device tree node that clearly describes the
> > entire topology. This saves the trouble of scanning individual
On Mon, Jun 24, 2019 at 3:57 PM Atish Patra wrote:
>
> Currently, there is no cpu topology defined in RISC-V.
> Define a device tree node that clearly describes the
> entire topology. This saves the trouble of scanning individual
> cache to figure out the topology.
>
> Here is the linux kernel
Currently, there is no cpu topology defined in RISC-V.
Define a device tree node that clearly describes the
entire topology. This saves the trouble of scanning individual
cache to figure out the topology.
Here is the linux kernel patch series that enables topology
for RISC-V.
