CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/11/26 09:01:34
Modified files:
target-mips: translate.c
Log message:
Micro-optimize back-to-back store-load sequences.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/11/22 15:10:22
Modified files:
target-mips: translate.c
Log message:
Optimize the conventional move operation.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/11/08 16:44:01
Modified files:
target-mips: translate.c
Log message:
Formatting fix.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/10/23 13:15:33
Modified files:
target-mips: translate.c
Log message:
Switch bc1any* instructions off if no MIPS-3D is implemented.
CVSWeb URLs:
Thiemo Seufer a écrit :
CVSROOT: /sources/qemu
Module name: qemu
Changes by: Thiemo Seufer ths 07/10/23 13:15:33
Modified files:
target-mips: translate.c
Log message:
Switch bc1any* instructions off if no MIPS-3D is implemented.
CVSWeb URLs:
Aurelien Jarno wrote:
Thiemo Seufer a écrit :
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/10/23 13:15:33
Modified files:
target-mips: translate.c
Log message:
Switch bc1any* instructions off if no MIPS-3D is implemented.
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/10/24 00:52:08
Modified files:
target-mips: translate.c
Log message:
Remove bogus instruction decode.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/09/26 23:50:39
Modified files:
target-mips: translate.c
Log message:
Wrap a few often used tests with unlikely(), by Aurelien Jarno.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/06/01 17:47:07
Modified files:
target-mips: translate.c
Log message:
Make sure hflags are updated for CP0_Status changes.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/06/02 00:25:12
Modified files:
target-mips: translate.c
Log message:
Check for R2 instructions, and throw RI if we don't emulate R2.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/31 23:42:46
Modified files:
target-mips: translate.c
Log message:
Simplify code.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/19 17:44:34
Modified files:
target-mips: translate.c
Log message:
Fix ldl/ldr implementation, by Aurelien Jarno.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/13 14:42:19
Modified files:
target-mips: translate.c
Log message:
Don't decode CP0 XContext on 32bit MIPS.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/11 10:43:55
Modified files:
target-mips: translate.c
Log message:
Another bit of nicer debug output.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/11 00:16:06
Modified files:
target-mips: translate.c
Log message:
Improved debug output for the MIPS opcode decoder.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/05/10 00:51:01
Modified files:
target-mips: translate.c
Log message:
Fix for the scd instruction, by Aurelien Jarno.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/25 13:58:52
Modified files:
target-mips: translate.c
Log message:
Fix lui sign extension.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/15 19:52:12
Modified files:
target-mips: translate.c
Log message:
Small code generation optimization.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/16 01:35:30
Modified files:
target-mips: translate.c
Log message:
Simplify branch likely handling.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/11 20:34:23
Modified files:
target-mips: translate.c translate_init.c
Log message:
Make SYNCI_Step and CCRes CPU-specific.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/11 02:15:08
Modified files:
target-mips: translate.c
Log message:
Code formatting fix.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/09 12:31:31
Modified files:
target-mips: translate.c
Log message:
Remove bogus mtc0 handling.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/07 01:10:22
Modified files:
target-mips: translate.c
Log message:
Actually skip over delay slot for a non-taken branch likely.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/07 01:11:15
Modified files:
target-mips: translate.c
Log message:
Set proper BadVAddress value for unaligned instruction fetch.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/07 01:11:39
Modified files:
target-mips: translate.c
Log message:
Implement prefx.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/04 21:07:17
Modified files:
target-mips: translate.c
Log message:
Fix code formatting.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/04/02 17:28:07
Modified files:
target-mips: translate.c
Log message:
MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registers
are implemented.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 07/03/19 22:15:30
Modified files:
target-mips: translate.c
Log message:
Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 06/12/16 16:45:18
Modified files:
target-mips: translate.c
Log message:
Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi
Nemoto.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 06/12/06 23:12:49
Modified files:
target-mips: translate.c
Log message:
Update copyright notice.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Changes by: Thiemo Seufer ths 06/12/07 00:30:19
Modified files:
target-mips: translate.c
Log message:
Simplify mask construction.
CVSWeb URLs:
CVSROOT:/sources/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard [EMAIL PROTECTED] 06/04/23 15:21:24
Modified files:
target-mips: translate.c
Log message:
MIPS CP0 not usable in kernel mode (Stefan Weil)
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 15:10:44
Modified files:
target-mips: translate.c
Log message:
fixed jump mask (Ralf Baechle)
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 15:20:06
Modified files:
target-mips: translate.c
Log message:
unaligned load fix (Ralf Baechle)
CVSWeb URLs:
CVSROOT:/cvsroot/qemu
Module name:qemu
Branch:
Changes by: Fabrice Bellard [EMAIL PROTECTED] 05/07/02 15:28:16
Modified files:
target-mips: translate.c
Log message:
report C0 status correctly (Ralf Baechle)
CVSWeb URLs:
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