Re: [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

LIU Zhiwei 於 2021年4月9日 週五 下午3:52寫道： > The xip CSR appears hardwired to zero in CLIC mode, replaced by separate > memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be > ignored and will not trap (i.e., no access faults). > > Signed-off-by: LIU Zhiwei --- > target/riscv/csr.c

[RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei --- target/riscv/csr.c | 10 ++ 1 file changed, 10 insertions(+)