Re: [RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions

On 8/17/20 1:49 AM, frank.ch...@sifive.com wrote: > +static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, > +uint8_t eew) > { > -return !s->vill; > +uint8_t lmul_r = s->lmul < 0 ? 0 : s->lmul; > +int8_t emul = ctzl(eew) - (s->sew +

[RFC v4 19/70] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 67 target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.inc.c | 193 target/riscv/vector_helper.c| 89 ++- 4 files