> -Original Message-
> From: Qemu-devel
> On Behalf Of Anton Johansson via
...
> Hi, Brian!
>
> I've taken a look and most of this patch seems good, however I have a few
> comments/observations.
Anton, sorry I missed this message last week, only following up now.
> > Some registers
On 9/6/22 23:26, Taylor Simpson wrote:
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index
8a334ba07b..21385f556e 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
static inline void gen_log_reg_write(int rnum, TCGv val) {
-
> -Original Message-
> From: Brian Cain
> Sent: Thursday, September 1, 2022 4:30 PM
> To: qemu-devel@nongnu.org; Taylor Simpson
> Cc: Richard Henderson ; Brian Cain
>
> Subject: [PATCH] Hexagon (target/hexagon) implement mutability mask for
> GPRs
>
> Some registers are defined to
> -Original Message-
> From: Richard Henderson
...
> It might be clearer, and easier to initialize, if you invert the sense of the
> mask:
Ok -- thanks for the suggestions! I'll give 'em all a try.
-Brian
On 9/1/22 22:29, Brian Cain wrote:
+void gen_masked_reg_write(TCGv cur_val, TCGv in_val, TCGv out_val,
+target_ulong reg_mask) {
+TCGv set_bits = tcg_temp_new();
+TCGv cleared_bits = tcg_temp_new();
+
+/*
+ * set_bits = in_val & reg_mask
+ * cleared_bits = (~in_val) &
Hi, Brian!
I've taken a look and most of this patch seems good, however I have a few
comments/observations.
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Brian Cain
---
target/hexagon/gen_masked.c | 44
