Re: [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor

2020-07-07 Thread Jason Wang
On 2020/7/4 下午4:07, Liu Yi L wrote: In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor Typo. from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should be 5 when descriptor

RE: [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor

2020-07-06 Thread Liu, Yi L
> From: Peter Xu > Sent: Tuesday, July 7, 2020 4:58 AM > > On Sat, Jul 04, 2020 at 01:07:15AM -0700, Liu Yi L wrote: > > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was > > introduced in VTD_IQA_REG. Sfotware could set this bit to tell VT-d > > the QI descriptor from software would

Re: [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor

2020-07-06 Thread Peter Xu
On Sat, Jul 04, 2020 at 01:07:15AM -0700, Liu Yi L wrote: > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced > in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor > from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should > be 5 when