Re: [Qemu-devel] [PATCH 2/4] bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block

On 27 February 2016 at 00:16, Andrew Baumann wrote: This bit of the commit message is a good place to list the "not yet implemented" parts of the device. > Signed-off-by: Andrew Baumann > --- > +/* > + * BCM2835 (Raspberry Pi / Pi 2)

Re: [Qemu-devel] [V6 0/4] AMD IOMMU

On Tue, Mar 01, 2016 at 09:17:58PM +0100, Jan Kiszka wrote: > On 2016-03-01 21:11, Michael S. Tsirkin wrote: > > On Tue, Mar 01, 2016 at 03:00:09PM +0100, Jan Kiszka wrote: > >> On 2016-03-01 14:48, Jan Kiszka wrote: > >>> There is likely no way around write-protecting the IOMMU page tables (in >

Re: [Qemu-devel] [PATCH v4 0/9] NVDIMM ACPI: introduce the framework of QEMU emulated

On Tue, Mar 01, 2016 at 06:56:02PM +0800, Xiao Guangrong wrote: > This patchset is against commit 2212ef27b342b98b220fe9 (fw-cfg: support > writeable blobs) on pci branch of Michael's git tree > and can be found at: > https://github.com/xiaogr/qemu.git nvdimm-acpi-v4 Applied patch 1-3 and

Re: [Qemu-devel] [V6 0/4] AMD IOMMU

On Tue, Mar 01, 2016 at 03:00:09PM +0100, Jan Kiszka wrote: > On 2016-03-01 14:48, Jan Kiszka wrote: > > There is likely no way around write-protecting the IOMMU page tables (in > > KVM mode) once we evaluated and cached them somewhere. > > I mean, when in kvm mode AND having something that

Re: [Qemu-devel] [V6 0/4] AMD IOMMU

On 2016-03-01 21:11, Michael S. Tsirkin wrote: > On Tue, Mar 01, 2016 at 03:00:09PM +0100, Jan Kiszka wrote: >> On 2016-03-01 14:48, Jan Kiszka wrote: >>> There is likely no way around write-protecting the IOMMU page tables (in >>> KVM mode) once we evaluated and cached them somewhere. >> >> I

Re: [Qemu-devel] [PATCH v2 15/15] tests/docker/Makefile.include: snapshot the src for docker

Fam Zheng writes: > From: Alex Bennée > > Instead of providing a live version of the source tree to the docker > container we snapshot it with git-archive. This ensure the tree is in a > pristine state for whatever operations the container is going to

Re: [Qemu-devel] [PATCH v1 00/17] ARM big-endian and setend support

On Mon, Feb 29, 2016 at 9:27 PM, Stefan Weil wrote: > Am 18.01.2016 um 08:12 schrieb Peter Crosthwaite: >> Hi All, >> >> This patch series adds system-mode big-endian support for ARM. It also >> implements the setend instruction, and loading of BE binaries even in >> LE

[Qemu-devel] qemu AIO worker threads change causes Guest OS hangup

Hi all, I’m trying to add some latency conditionally to I/O requests (qemu_paiocb, from **IDE** disk emulation, **raw** image file). My idea is to add this part into the work thread: * First, set a timer for each incoming qemu_paiocb structure (e.g. 2ms) * When worker thread handles this

Re: [Qemu-devel] Migration design planning

Of course I have a nasty habit of responding before seeing replies, apologies. On 03/01/2016 10:24 AM, Vladimir Sementsov-Ogievskiy wrote: > On 01.03.2016 16:47, Juan Quintela wrote: >> John Snow wrote: >>> Hi Juan; >>> We need your assistance in reviewing two competing designs

Re: [Qemu-devel] [PATCH v2 0/9] Add i.MX6 (Single/Dual/Quad) support

Peter, Can I merge the 2 i.MX series as one depend on the other. Thanks JC Le 28/02/2016 21:27, Jean-Christophe DUBOIS a écrit : Peter, Are you OK if I merge the 2 series (i.MX6 and SPI for i.MX6) into a single series? Thanks. JC Le 08/02/2016 23:08, Jean-Christophe Dubois a écrit :

Re: [Qemu-devel] [PATCH 3/4] bcm2835_fb: add framebuffer device for Raspberry Pi

On 27 February 2016 at 00:16, Andrew Baumann wrote: > The framebuffer occupies the upper portion of memory (64MiB by > default), but it can only be controlled/configured via a system > mailbox or property channel (to be added by a subsequent patch). > >

Re: [Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions

On 03/01/2016 08:24 AM, Bastian Koppelmann wrote: > +env->FPU_FS = 0; > +if (get_float_exception_flags(>fp_status) & float_flag_invalid) { > +env->FPU_FI = (1 << 31); > +env->FPU_FS = 1; > +} > + > +if (get_float_exception_flags(>fp_status) & float_flag_inexact) { >

Re: [Qemu-devel] [PATCH] Use special code for sigsetjmp only in cpu-exec.c

Am 01.03.2016 um 18:54 schrieb Peter Maydell: > On 1 March 2016 at 17:53, Paolo Bonzini wrote: >> >> >> On 01/03/2016 18:46, Andrew Baumann wrote: >>> --- a/include/sysemu/os-win32.h >>> +++ b/include/sysemu/os-win32.h >>> @@ -60,6 +60,7 @@ >>> * If this parameter is NULL,

Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation.

Le 01/03/2016 17:19, Peter Maydell a écrit : On 29 February 2016 at 21:32, Jean-Christophe DUBOIS wrote: Le 29/02/2016 22:14, Peter Maydell a écrit : Is there a datasheet available for this? Well the SRC device is described in the i.MX6 reference manual.

Re: [Qemu-devel] [PATCH 4/4] bcm2835_property: implement framebuffer control/configuration properties

On 27 February 2016 at 00:16, Andrew Baumann wrote: > The property channel driver now interfaces with the framebuffer device > to query and set framebuffer parameters. As a result of this, the "get > ARM RAM size" query now correctly returns the video RAM base

Re: [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

On 01.03.2016 20:42, Peter Maydell wrote: The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU

Re: [Qemu-devel] [QEMU] Windows XP / Windows 95 / MS-DOS 6 regressions

Le 01/03/2016 16:12, Paolo Bonzini a écrit : On 28/02/2016 22:49, Hervé Poussineau wrote: 3) MS-DOS 6 freezes when loading himem.sys since commit: commit 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Author: Richard Henderson Date: Thu Jul 2 13:59:21 2015 +0100

[Qemu-devel] [PATCH] target-i386: Fix SMSW for 64-bit mode

In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Signed-off-by: Richard Henderson --- target-i386/translate.c | 14 -- 1 file changed, 8 insertions(+), 6

Re: [Qemu-devel] [PATCH] target-i386: fix interrupt shadow

Le 01/03/2016 15:09, Paolo Bonzini a écrit : The handling of the interrupt shadow is subtle. QEMU's check to stop the interrupt shadow needs to check the state after the _penultimate_ instruction. Because the interrupt shadow is only enabled at the end of a translation block, and it makes the

Re: [Qemu-devel] Migration design planning

On 03/01/2016 08:47 AM, Juan Quintela wrote: > John Snow wrote: >> Hi Juan; >> We need your assistance in reviewing two competing designs for migrating >> some block data so we can move forward with the feature. >> >> First, some background: >> >> What: Block Dirty Bitmaps.

Re: [Qemu-devel] [PATCH v2 0/9] Add i.MX6 (Single/Dual/Quad) support

On 1 March 2016 at 19:18, Jean-Christophe DUBOIS wrote: > Peter, > > Can I merge the 2 i.MX series as one depend on the other. Yes, go ahead. thanks -- PMM

Re: [Qemu-devel] [RFC PATCH v3 0/9] vfio: capability chains, sparse mmap, device specific regions, IGD support

github.com/awilliam/qemu-vfio/tree/vfio-igd-20160301

Re: [Qemu-devel] [PATCH v1 00/17] ARM big-endian and setend support

On Mon, Feb 29, 2016 at 9:27 PM, Stefan Weil wrote: > Am 18.01.2016 um 08:12 schrieb Peter Crosthwaite: >> Hi All, >> >> This patch series adds system-mode big-endian support for ARM. It also >> implements the setend instruction, and loading of BE binaries even in >> LE

Re: [Qemu-devel] [PATCH] target-i386: fix smsw and lmsw from/to register

Le 01/03/2016 16:12, Paolo Bonzini a écrit : SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386: Rearrange processing of 0F 01", 2016-02-13) did not account for that. Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Cc: r...@twiddle.net Reported-by: Hervé Poussineau

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On 03/01/2016 05:12 PM, Programmingkid wrote: >> >>> + >>> +[MAC_KEY_ESC] = Q_KEY_CODE_ESC, >>> +//[MAC_KEY_F1] = Q_KEY_CODE_POWER, // Just in case you need the power >>> key >>> +[MAC_KEY_F1] = Q_KEY_CODE_F1, >> >> The comment looks weird. Probably worth a mention in the commit

Re: [Qemu-devel] [Qemu-arm] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model

Hi Peter, On Thu, 2016-02-25 at 16:29 +, Peter Maydell wrote: > On 16 February 2016 at 11:34, Andrew Jeffery wrote: > > Implement a minimal ASPEED AVIC device model, enough to boot a Linux > > kernel configured with aspeed_defconfig. The VIC implements the 'new' > >

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On Mar 1, 2016, at 7:25 PM, Eric Blake wrote: > On 03/01/2016 05:12 PM, Programmingkid wrote: > >>> + +[MAC_KEY_ESC] = Q_KEY_CODE_ESC, +//[MAC_KEY_F1] = Q_KEY_CODE_POWER, // Just in case you need the power key +[MAC_KEY_F1] = Q_KEY_CODE_F1, >>> >>> The

Re: [Qemu-devel] [RFC PATCH v0 4/6] spapr: CPU hotplug support

On Tue, Mar 01, 2016 at 01:28:56PM +0530, Bharata B Rao wrote: > On Mon, Feb 29, 2016 at 10:12:10AM +0530, Bharata B Rao wrote: > > > > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > > > > index b7c5ebd..cc0369e 100644 > > > > --- a/hw/ppc/spapr_rtas.c > > > > +++ b/hw/ppc/spapr_rtas.c >

Re: [Qemu-devel] [PATCH v3 1/2] generic-loader: Add a generic loader

On 1 March 2016 at 23:56, Alistair Francis wrote: > On Fri, Feb 26, 2016 at 8:22 AM, Peter Maydell > wrote: >> Writing directly to cpu->as is not very generic. In particular, >> how should this interact with TrustZone, where you might want

[Qemu-devel] [PATCH] bcm2835_mbox/property: replace ldl_phys/stl_phys with endian-specific accesses

PMM pointed out that ldl_phys and stl_phys are dependent on the CPU's endianness, whereas device model code should be independent of it. This changes the relevant Raspberry Pi devices to explicitly call the little-endian variants. Signed-off-by: Andrew Baumann ---

Re: [Qemu-devel] [PATCH v3 1/2] generic-loader: Add a generic loader

On Tue, Mar 1, 2016 at 4:07 PM, Peter Maydell wrote: > On 1 March 2016 at 23:56, Alistair Francis > wrote: >> On Fri, Feb 26, 2016 at 8:22 AM, Peter Maydell >> wrote: > >>> Writing directly to cpu->as is not very

Re: [Qemu-devel] [PATCH v3 1/2] generic-loader: Add a generic loader

On Fri, Feb 26, 2016 at 8:22 AM, Peter Maydell wrote: > On 19 February 2016 at 20:40, Alistair Francis > wrote: >> Add a generic loader to QEMU which can be used to load images or set >> memory values. > > I'm not inherently opposed to this

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On Mar 1, 2016, at 6:18 PM, Peter Maydell wrote: > On 1 March 2016 at 22:12, Programmingkid wrote: >> The old pc/xt keyboard keycode array is replaced with QEMU's own QKeyCode >> layout. >> >> Signed-off-by: John Arbuckle >> >> --- >>

Re: [Qemu-devel] [PATCH] target-ppc: fix sync of SPR_SDR1 with KVM

On Tue, Mar 01, 2016 at 07:03:10PM +0100, Greg Kurz wrote: > The gdbstub can't access guest memory with current master. This is what you > get in gdb: > > 0x19b8 in main (argc= at address 0x3fffce4d3620>, argv= at address 0x3fffce4d3628>) at fp.c:11 > > Bisect leads to the following

[Qemu-devel] Performance Profiling 2 VMs

Hi All, I am new to qemu development. Sorry If this is not the correct forum for this question, it would be great if you could direct me to correct forum. I am seeing very low virtio network throughput on an older (2.6.18) linux guest vs another newer guest (3.10) both running on the same host.

[Qemu-devel] [PATCH v2] MacKeys.h: initial commit

This patch adds the file MacKeys.h. It is a file that contains all the constants for the Macintosh keyboard keycodes. Signed-off-by: John Arbuckle --- Added standard license. Added #ifndef #define #endif macros. include/hw/input/MacKeys.h | 168

Re: [Qemu-devel] [PATCH] MacKeys.h: initial commit

On 03/01/2016 04:08 PM, Peter Maydell wrote: > On 1 March 2016 at 22:07, Programmingkid wrote: >> This patch adds the file MacKeys.h. It is a file that contains all the >> constants >> for the Macintosh keyboard keycodes. >> >> Signed-off-by: John Arbuckle

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On 1 March 2016 at 22:12, Programmingkid wrote: > The old pc/xt keyboard keycode array is replaced with QEMU's own QKeyCode > layout. > > Signed-off-by: John Arbuckle > > --- > Maintainer note: > Please apply these patches before testing: > -

Re: [Qemu-devel] [PATCH] hw/input/adb.c: Replace pc_to_adb_keycode with more detailed array

On 1 March 2016 at 22:10, Programmingkid wrote: > The pc_to_adb_keycode array was not very easy to work with. The replacement > array number_to_adb_keycode list all the element indexes on the left and its > value on the right. This makes finding a particular index or

Re: [Qemu-devel] [PATCH] hw/input/adb.c: Replace pc_to_adb_keycode with more detailed array

On Mar 1, 2016, at 6:34 PM, Peter Maydell wrote: > On 1 March 2016 at 22:10, Programmingkid wrote: >> The pc_to_adb_keycode array was not very easy to work with. The replacement >> array number_to_adb_keycode list all the element indexes on the left and its >> value

[Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

The old pc/xt keyboard keycode array is replaced with QEMU's own QKeyCode layout. Signed-off-by: John Arbuckle --- Maintainer note: Please apply these patches before testing: - qapi-schema.json: Add kp_equals and power keys - adb.c: Replace pc_to_adb_keycode with

[Qemu-devel] [PATCH v3 04/12] i.MX: Add the CLK_IPG_HIGH clock

EPIT, GPT and other i.MX timers are using "abstract" clocks among which a CLK_IPG_HIGH clock. On i.MX25 and i.MX31 CLK_IPG and CLK_IPG_HIGH are mapped to the same clock but on other SOC like i.MX6 they are mapped to distinct clocks. This patch add the CLK_IPG_HIGH to prepare for SOC where these

[Qemu-devel] [PATCH v3 01/12] i.MX: Allow GPT timer to rollover.

GPT timer need to rollover when it reaches 0x. It also need to reset to 0 when in "restart mode" and crossing the compare 1 register. Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * None

[Qemu-devel] [PATCH v3 11/12] i.MX: Add i.MX6 SOC implementation.

For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Signed-off-by:

[Qemu-devel] [PATCH v3 12/12] i.MX: Add sabrelite i.MX6 emulation.

The sabrelite supports one SPI FLASH memory on SPI1 Signed-off-by: Jean-Christophe Dubois --- Changes since v1: * output a message and exit if RAM size is unsupported. Changes since v2: * Added include "qemu/osdep.h" * Added access to controllers through properties.

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On 03/01/2016 03:12 PM, Programmingkid wrote: > The old pc/xt keyboard keycode array is replaced with QEMU's own QKeyCode > layout. > > Signed-off-by: John Arbuckle > > --- > Maintainer note: > Please apply these patches before testing: > - qapi-schema.json: Add

Re: [Qemu-devel] [PATCH] qapi-schema.json: Add kp_equals and power keys

On 03/01/2016 03:33 PM, Programmingkid wrote: > > On Mar 1, 2016, at 5:23 PM, Gerd Hoffmann wrote: > >> On Di, 2016-03-01 at 17:04 -0500, Programmingkid wrote: >>> Add kp_equals and power keys support to the QKeyCode enum of keys. >> >> Please update the documentation in the comment too, so we

Re: [Qemu-devel] [PATCH] ui/cocoa.m: Replace pc/xt keyboard keycode array with QKeyCode

On Mar 1, 2016, at 6:16 PM, Eric Blake wrote: > On 03/01/2016 03:12 PM, Programmingkid wrote: >> The old pc/xt keyboard keycode array is replaced with QEMU's own QKeyCode >> layout. >> >> Signed-off-by: John Arbuckle >> >> --- >> Maintainer note: >> Please apply

Re: [Qemu-devel] [PATCH 3/4] bcm2835_fb: add framebuffer device for Raspberry Pi

> From: Peter Maydell [mailto:peter.mayd...@linaro.org] > Sent: Tuesday, 1 March 2016 11:23 AM > > On 27 February 2016 at 00:16, Andrew Baumann > wrote: > > The framebuffer occupies the upper portion of memory (64MiB by > > default), but it can only be

[Qemu-devel] [PATCH v2] qapi-schema.json: Add kp_equals and power keys

Add kp_equals and power keys support to the QKeyCode enum of keys. Signed-off-by: John Arbuckle --- Added comment about kp_equals and power keys. qapi-schema.json |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/qapi-schema.json

[Qemu-devel] [PULL 1/5] console: add & use qemu_console_lookup_by_device_name

We have two places needing this, and a third one will come shortly. So factor things out into a helper function to reduce code duplication. Signed-off-by: Gerd Hoffmann Reviewed-by: Daniel P. Berrange Reviewed-by: Markus Armbruster ---

Re: [Qemu-devel] [PATCH v3 5/8] nvdimm acpi: introduce patched dsm memory

On Tue, Mar 01, 2016 at 04:53:23PM +0800, Xiao Guangrong wrote: > > > On 02/29/2016 05:38 PM, Michael S. Tsirkin wrote: > > >+/* Build NAME(, 0x) where 0x is encoded as a dword, > >+ * and return the offset to 0x for runtime patching. > >+ * > >+ * Warning: runtime

[Qemu-devel] [PATCH qemu v13 10/16] vfio: Use different page size for different IOMMU types

The existing memory listener is called on RAM or PCI address space which implies potentially different page size. This uses new memory_region_iommu_get_page_sizes() for IOMMU regions or falls back to qemu_real_host_page_size if RAM. Signed-off-by: Alexey Kardashevskiy ---

[Qemu-devel] [PATCH qemu v13 01/16] memory: Fix IOMMU replay base address

Since a788f227 "memory: Allow replay of IOMMU mapping notifications" when new VFIO listener is added, all existing IOMMU mappings are replayed. However there is a problem that the base address of an IOMMU memory region (IOMMU MR) is ignored which is not a problem for the existing user (which is

[Qemu-devel] [PATCH qemu v13 06/16] spapr_pci: Reset DMA config on PHB reset

LoPAPR dictates that during system reset all DMA windows must be removed and the default DMA32 window must be created so does the patch. At the moment there is just one window supported so no change in behaviour is expected. Signed-off-by: Alexey Kardashevskiy ---

Re: [Qemu-devel] [RFC PATCH v0 2/6] spapr: CPU core device

On Tue, 1 Mar 2016 12:21:27 +1100 David Gibson wrote: > On Mon, Feb 29, 2016 at 04:15:25PM +0100, Igor Mammedov wrote: > > On Mon, 29 Feb 2016 18:25:25 +0530 > > Bharata B Rao wrote: > > > On Mon, Feb 29, 2016 at 11:03:16AM +0100, Igor

Re: [Qemu-devel] [PATCH v2 02/15] Makefile: Rules for docker testing

Fam Zheng writes: > On Mon, 02/29 17:08, Alex Bennée wrote: >> >> Fam Zheng writes: >> >> > This adds a group of make targets to run docker tests, all are available >> > in source tree without running ./configure. >> > >> > The usage is shown by "make docker".

Re: [Qemu-devel] [RFC PATCH v0 4/6] spapr: CPU hotplug support

On Mon, Feb 29, 2016 at 10:12:10AM +0530, Bharata B Rao wrote: > > > diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c > > > index b7c5ebd..cc0369e 100644 > > > --- a/hw/ppc/spapr_rtas.c > > > +++ b/hw/ppc/spapr_rtas.c > > > @@ -34,6 +34,7 @@ > > > > > > #include "hw/ppc/spapr.h" > > >

[Qemu-devel] [PATCH qemu v13 16/16] spapr_pci/spapr_pci_vfio: Support Dynamic DMA Windows (DDW)

This adds support for Dynamic DMA Windows (DDW) option defined by the SPAPR specification which allows to have additional DMA window(s) This implements DDW for emulated and VFIO devices. As all TCE root regions are mapped at 0 and 64bit long (and actual tables are child regions), this replaces

Re: [Qemu-devel] [PATCH v2 00/16] qapi: Allow blockdev-add for NBD

Am 01.03.2016 um 11:00 hat Daniel P. Berrange geschrieben: > On Tue, Mar 01, 2016 at 12:37:14AM +0100, Max Reitz wrote: > > On 01.03.2016 00:24, Eric Blake wrote: > > > On 02/29/2016 04:19 PM, Max Reitz wrote: > > >> Turns out NBD is not so simple to do if you do it right. Anyway, this > > >>

Re: [Qemu-devel] [RFC PATCH v0 2/6] spapr: CPU core device

On Mon, Feb 29, 2016 at 04:15:25PM +0100, Igor Mammedov wrote: > On Mon, 29 Feb 2016 18:25:25 +0530 > Bharata B Rao wrote: > > > On Mon, Feb 29, 2016 at 11:03:16AM +0100, Igor Mammedov wrote: > > > On Mon, 29 Feb 2016 11:20:19 +0530 > > > Bharata B Rao

[Qemu-devel] [PATCH qemu v13 09/16] vfio: Generalize IOMMU memory listener

At the moment VFIOContainer uses one memory listener which listens on PCI address space for both Type1 and sPAPR IOMMUs. Soon we will need another listener to listen on RAM; this will do DMA memory pre-registration for sPAPR guests which basically pins all guest pages in the host physical RAM.

[Qemu-devel] [PATCH qemu v13 15/16] vfio: Move iova_pgsizes from container to guest IOMMU

The page size is an attribute of an IOMMU, not a container as a container may contain more just one IOMMU. This moves iova_pgsizes from VFIOContainer to VFIOGuestIOMMU. The following patch will use this. This removes iova_pgsizes from Type1 IOMMU as it is not used there anyway and when it will

[Qemu-devel] [PATCH qemu v13 12/16] vmstate: Define VARRAY with VMS_ALLOC

This allows dynamic allocation for migrating arrays. Already existing VMSTATE_VARRAY_UINT32 requires an array to be pre-allocated, however there are cases when the size is not known in advance and there is no real need to enforce it. This defines another variant of VMSTATE_VARRAY_UINT32 with

[Qemu-devel] [PATCH qemu v13 14/16] spapr_pci: Add and export DMA resetting helper

This will be later used by the "ibm,reset-pe-dma-window" RTAS handler which resets the DMA configuration to the defaults. Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr_pci.c | 11 --- include/hw/pci-host/spapr.h | 2 ++ 2 files changed, 10 insertions(+),

Re: [Qemu-devel] [RFC PATCH v0 5/6] qmp, spapr: Show hot-plugged/pluggable CPU slots in the Machine

On Mon, Feb 29, 2016 at 11:46:42AM +0100, Igor Mammedov wrote: > On Thu, 25 Feb 2016 21:52:41 +0530 > Bharata B Rao wrote: > > > Implement query cpu-slots that provides information about hot-plugged > > as well as hot-pluggable CPU slots that the machine supports. > >

Re: [Qemu-devel] [RFC PATCH v0 2/6] spapr: CPU core device

On Tue, Mar 01, 2016 at 10:16:18AM +0100, Igor Mammedov wrote: > On Tue, 1 Mar 2016 13:47:27 +0530 > Bharata B Rao wrote: > > > On Mon, Feb 29, 2016 at 04:15:25PM +0100, Igor Mammedov wrote: > > > On Mon, 29 Feb 2016 18:25:25 +0530 > > > Bharata B Rao

Re: [Qemu-devel] [PATCH] Use special code for sigsetjmp only in cpu-exec.c

On 1 March 2016 at 05:07, Stefan Weil wrote: > The rest of the code can use longjmp with stack unwinding. > > Signed-off-by: Stefan Weil > --- > > This is a bug fix needed for 64 bit Windows. > > QEMU for Windows currently gets the wrong definition for >

[Qemu-devel] [PULL 2/5] qapi: switch x-input-send-event from console to device+head

Use display device qdev id and head number instead of console index to specify the QemuConsole. This makes things consistent with input devices (for input routing) and vnc server configuration, which both use display and head too. Signed-off-by: Gerd Hoffmann Reviewed-by:

[Qemu-devel] [PULL 5/5] qapi: promote input-send-event to stable

With all fixups being in place now, we can promote input-send-event to stable abi by removing the x- prefix. Signed-off-by: Gerd Hoffmann Reviewed-by: Markus Armbruster Reviewed-by: Eric Blake --- qapi-schema.json | 12 +++-

Re: [Qemu-devel] [PATCH v3 5/8] nvdimm acpi: introduce patched dsm memory

On 02/29/2016 05:38 PM, Michael S. Tsirkin wrote: On Sun, Feb 14, 2016 at 04:51:02PM +0800, Xiao Guangrong wrote: The dsm memory is used to save the input parameters and store the dsm result which is filled by QEMU. The address of dsm memory is decided by bios and patched into int32 object

Re: [Qemu-devel] [PATCH v3 5/8] nvdimm acpi: introduce patched dsm memory

On 02/29/2016 05:38 PM, Michael S. Tsirkin wrote: +/* Build NAME(, 0x) where 0x is encoded as a dword, + * and return the offset to 0x for runtime patching. + * + * Warning: runtime patching is best avoided. Only use this as + * a replacement for DataTableRegion

[Qemu-devel] [PATCH qemu v13 00/16] spapr: vfio: Enable Dynamic DMA windows (DDW)

Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus where devices are allowed to do DMA. These ranges are called DMA windows. By default, there is a single DMA window, 1 or 2GB big, mapped at zero on a PCI bus. PAPR defines a DDW RTAS API which allows pseries guests

[Qemu-devel] [PATCH qemu v13 04/16] spapr_iommu: Introduce "enabled" state for TCE table

Currently TCE tables are created once at start and their sizes never change. We are going to change that by introducing a Dynamic DMA windows support where DMA configuration may change during the guest execution. This changes spapr_tce_new_table() to create an empty zero-size IOMMU memory region

[Qemu-devel] [PATCH qemu v13 03/16] spapr_iommu: Move table allocation to helpers

At the moment presence of vfio-pci devices on a bus affect the way the guest view table is allocated. If there is no vfio-pci on a PHB and the host kernel supports KVM acceleration of H_PUT_TCE, a table is allocated in KVM. However, if there is vfio-pci and we do yet not KVM acceleration for

[Qemu-devel] [PATCH qemu v13 02/16] spapr_pci: Move DMA window enablement to a helper

We are going to have multiple DMA windows soon so let's start preparing. This adds a new helper to create a DMA window and makes use of it in sPAPRPHBState::realize(). Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr_pci.c | 40 +++- 1

Re: [Qemu-devel] [RFC PATCH v0 0/6] Core based CPU hotplug for PowerPC sPAPR

On Thu, Feb 25, 2016 at 09:52:36PM +0530, Bharata B Rao wrote: > Hi, > > This is an attempt to implement CPU hotplug for PowerPC sPAPR based on > the approach suggested by Andreas. While I say that, I should also explicitly > add that I have tried to follow Andreas' suggestions to the best of my

Re: [Qemu-devel] [PATCH v2 00/16] qapi: Allow blockdev-add for NBD

On Tue, Mar 01, 2016 at 12:37:14AM +0100, Max Reitz wrote: > On 01.03.2016 00:24, Eric Blake wrote: > > On 02/29/2016 04:19 PM, Max Reitz wrote: > >> Turns out NBD is not so simple to do if you do it right. Anyway, this > >> series adds blockdev-add support for NBD clients. > >> > >> Patches 1 and

[Qemu-devel] [PATCH qemu v13 07/16] vfio, memory: Notify IOMMU about starting/stopping being used by VFIO

This adds a vfio_votify() callback to inform an IOMMU (and then its owner) that VFIO started using the IOMMU. This is used by the pseries machine to enable/disable in-kernel acceleration of TCE hypercalls. Signed-off-by: Alexey Kardashevskiy --- hw/ppc/spapr_iommu.c | 9

Re: [Qemu-devel] [PATCH v3 5/8] nvdimm acpi: introduce patched dsm memory

On 03/01/2016 05:08 PM, Michael S. Tsirkin wrote: On Tue, Mar 01, 2016 at 04:53:23PM +0800, Xiao Guangrong wrote: On 02/29/2016 05:38 PM, Michael S. Tsirkin wrote: +/* Build NAME(, 0x) where 0x is encoded as a dword, + * and return the offset to 0x for runtime

Re: [Qemu-devel] [PATCH v2 0/7] memory: Clean up MemoryRegion.ram_addr and optimize address_space_translate

On 01/03/2016 07:18, Fam Zheng wrote: > v2: In the optimization patch, factor out section_covers_addr() and use it. > [Paolo, Peter] > Check "ram_block == NULL" in patch 3. [Gonglei] > Add Gonglei's rev-by in patches 1, 2, 4 and 5. > > The first four patches drop ram_addr from

Re: [Qemu-devel] [PATCH v2 6/7] exec: Factor out section_covers_addr

On 01/03/2016 07:18, Fam Zheng wrote: > +/* Memory topology clips a memory region to 2^64, size.hi >= 0 means the > + * section must cover any addr. */ Small improvement: /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means * the section must cover the

Re: [Qemu-devel] [PATCH] pxb: cleanup

On 03/01/2016 11:45 AM, Cao jin wrote: Signed-off-by: Cao jin --- BTW: this doc seems little out of date, since pxb has already support Q35. Hi, Yes, you are right, but we use a different device, pxb-pcie. I will send a doc update about it, thanks for reminding me,

Re: [Qemu-devel] [PATCH v2 03/15] docker: Add images

Fam Zheng writes: > On Mon, 02/29 17:18, Alex Bennée wrote: >> >> Fam Zheng writes: >> >> > Signed-off-by: Fam Zheng >> >> I think we need to include the dtc libs in here unless we need to ship >> all submodules in the tree as well. > > OK,

[Qemu-devel] [PULL 1/1] seabios: update to 1.9.1 stable release

git shortlog rel-1.9.0..rel-1.9.1 = Cole Robinson (1): biostables: Support SMBIOS 2.6+ UUID format Kevin O'Connor (7): xhci: Check for device disconnects during USB2 reset polling xhci: Wait for port enable even for USB3 devices sdcard:

[Qemu-devel] [PULL 0/1] seabios: update to 1.9.1 stable release

9-1' into staging (2016-02-29 12:24:26 +) are available in the git repository at: git://git.kraxel.org/qemu tags/pull-seabios-20160301-1 for you to fetch changes up to fee5b753ff0eb8b25685227804a60dbc4a2ce6ea: seabios: update to 1.9.1 stable release (2016-03-01 09:37:07 +0

Re: [Qemu-devel] [RFC PATCH v0 2/6] spapr: CPU core device

On Tue, 1 Mar 2016 13:47:27 +0530 Bharata B Rao wrote: > On Mon, Feb 29, 2016 at 04:15:25PM +0100, Igor Mammedov wrote: > > On Mon, 29 Feb 2016 18:25:25 +0530 > > Bharata B Rao wrote: > > > > > On Mon, Feb 29, 2016 at 11:03:16AM +0100,

[Qemu-devel] [PATCH qemu v13 08/16] memory: Add reporting of supported page sizes

Every IOMMU has some granularity which MemoryRegionIOMMUOps::translate uses when translating, however this information is not available outside the translate context for various checks. This adds a get_page_sizes callback to MemoryRegionIOMMUOps and a wrapper for it so IOMMU users (such as VFIO)

Re: [Qemu-devel] [PATCH] pc-dimm: fix error handling in pc_dimm_check_memdev_is_busy()

On Mon, 29 Feb 2016 19:33:15 +0100 Markus Armbruster wrote: > Igor Mammedov writes: > > > if host_memory_backend_get_memory() were to return error and > > Start sentences with a capital letter, please. > > > NULL MemoryRegion,

[Qemu-devel] [PATCH v2] pc-dimm: fix error handling in pc_dimm_check_memdev_is_busy()

If host_memory_backend_get_memory() were to return error and NULL MemoryRegion, pc_dimm_check_memdev_is_busy() would crash dereferencing NULL pointer in memory_region_is_mapped(). But if error is set and non NULL MemoryRegion is returned then error_setg() will fail with "error already set"

[Qemu-devel] [PATCH qemu v13 11/16] vfio: spapr: Add SPAPR IOMMU v2 support (DMA memory preregistering)

This makes use of the new "memory registering" feature. The idea is to provide the userspace ability to notify the host kernel about pages which are going to be used for DMA. Having this information, the host kernel can pin them all once per user process, do locked pages accounting (once) and not

[Qemu-devel] [PATCH qemu v13 13/16] spapr_iommu: Remove need_vfio flag from sPAPRTCETable

sPAPRTCETable has a need_vfio flag which is passed to kvmppc_create_spapr_tce() and controls whether to create a guest view table in KVM as this depends on the host kernel ability to accelerate H_PUT_TCE for VFIO devices. We would set this flag at the moment when sPAPRTCETable is created in

[Qemu-devel] [PATCH qemu v13 05/16] spapr_iommu: Add root memory region

We are going to have multiple DMA windows at different offsets on a PCI bus. For the sake of migration, we will have as many TCE table objects pre-created as many windows supported. So we need a way to map windows dynamically onto a PCI bus when migration of a table is completed but at this stage

[Qemu-devel] [PATCH] pxb: cleanup

Signed-off-by: Cao jin --- BTW: this doc seems little out of date, since pxb has already support Q35. docs/pci_expander_bridge.txt| 6 +++--- hw/pci-bridge/pci_expander_bridge.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git

Re: [Qemu-devel] qemu AIO worker threads change causes Guest OS hangup

- Original Message - > From: "Huaicheng Li" > I’m trying to add some latency conditionally to I/O requests (qemu_paiocb, > from **IDE** disk emulation, **raw** image file). Paolo already covered the technical issue with what you're doing. Have you seen Linux

[Qemu-devel] [PATCH v3 05/12] i.MX: Add i.MX6 CCM and ANALOG device.

Reviewed-by: Peter Maydell Signed-off-by: Jean-Christophe Dubois --- Changes since V1: * move clk computation to uint64_t to avoid overflow * added explanation on _SET, _CLR and _TOG registers * move CCM and ANALOG handling in sub memory

Re: [Qemu-devel] [V6 0/4] AMD IOMMU

On Tue, Mar 01, 2016 at 10:23:55PM +0100, Jan Kiszka wrote: > On 2016-03-01 21:39, Michael S. Tsirkin wrote: > > On Tue, Mar 01, 2016 at 09:17:58PM +0100, Jan Kiszka wrote: > >> On 2016-03-01 21:11, Michael S. Tsirkin wrote: > >>> > >>> What this seems to call for is a new kind of protection > >>>

Re: [Qemu-devel] [PATCH v1 00/17] ARM big-endian and setend support

On 01/03/2016 19:43, Peter Crosthwaite wrote: > On Mon, Feb 29, 2016 at 9:27 PM, Stefan Weil wrote: >> It would be nice to get at least the emulation for 'setend' into the >> next version, because it is needed for the Raspberry Pi emulation. > > BTW if you can link me binaries

Re: [Qemu-devel] [PATCH v2] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR

On 1 March 2016 at 19:58, Sergey Fedorov wrote: > On 01.03.2016 20:42, Peter Maydell wrote: >> >> The GICv2 introduces a new CPU interface register GICC_DIR, which >> allows an OS to split the "priority drop" and "deactivate interrupt" >> parts of interrupt completion.

[Qemu-devel] [PATCH v7 2/6] s390x/cpu: Set initial CPU state in common routine

Both initial and hotplugged CPUs need to set the same initial state. Signed-off-by: Matthew Rosato Reviewed-by: David Hildenbrand --- hw/s390x/s390-virtio.c | 4 target-s390x/cpu.c | 2 ++ 2 files changed, 2 insertions(+), 4

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