From: Aleksandar Markovic
fpu/softfloat-specialize.h is the most critical file in SoftFloat
library, since it handles numerous differences between platforms in
relation to floating point arithmetics. This patch makes the code
in this file more consistent
From: Aleksandar Markovic
Function msa_reset() is updated so that flag snan_bit_is_one is
properly set to 0.
By applying this patch, a number of incorrect MSA behaviors that
require IEEE 754-2008 compliance will be fixed. Those are behaviors
that (up to the
On 10 June 2016 at 08:00, Amit Shah wrote:
> The following changes since commit 0c33682d5f29b0a4ae53bdec4c8e52e4fae37b34:
>
> target-i386: Move user-mode exception actions out of user-exec.c
> (2016-06-09 15:55:02 +0100)
>
> are available in the git repository at:
>
>
From: "Dr. David Alan Gilbert"
On the source, add a count of page requests received from the
destination.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Eric Blake
Reviewed-by: Denis V. Lunev
Message-Id:
From: "Daniel P. Berrange"
Recent migration QAPI enhancements had a few spelling mistakes
and also incorrect version number in a few places.
Signed-off-by: Daniel P. Berrange
Reviewed-by: Eric Blake
Message-Id:
From: "Dr. David Alan Gilbert"
Knowing whether the destination host supports migration with
postcopy can be tricky.
The destination doesn't need the capability set, however
if we set it then use the opportunity to do the test and
tell the user/management layer early.
On 9 June 2016 at 01:30, Alistair Francis wrote:
> On Thu, May 12, 2016 at 3:45 PM, Alistair Francis
> wrote:
>> This patch series is based on Peter C's original register API. His
>> original cover letter is below.
>
> Ping!
I've
From: "Dr. David Alan Gilbert"
This is a postcopy test (x86 only) that actually runs the guest
and checks the memory contents.
The test runs from an x86 boot block with the hex embedded in the test;
the source for this is:
...
.code16
.org 0x7c00
.file
On 8 June 2016 at 21:24, Laurent Vivier wrote:
> From: Laurent Vivier
>
> Parameter of SO_RCVTIMEO and SO_SNDTIMEO is timeval, not int.
>
> To test this, you can use :
>
> QEMU_STRACE= ping localhost 2>&1 |grep TIMEO
> 568
From: Thomas Huth
This is required for running QEMU on big endian hosts (like
PowerPC machines) that use RGB instead of BGR byte ordering.
Ticket: https://bugs.launchpad.net/qemu/+bug/1581796
Signed-off-by: Thomas Huth
Message-id:
Hi,
I've put together a wiki page on troubleshooting failed migrations;
see:
http://wiki.qemu.org/Features/Migration/Troubleshooting
Dave
--
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK
From: "Dr. David Alan Gilbert"
This is a postcopy test (x86 only) that actually runs the guest
and checks the memory contents.
The test runs from an x86 boot block with the hex embedded in the test;
the source for this is:
...
.code16
.org 0x7c00
.file
On Fri, Jun 10, 2016 at 09:15:44AM +0200, Igor Mammedov wrote:
> On Thu, 9 Jun 2016 15:34:30 -0300
> Eduardo Habkost wrote:
>
> > On Mon, Jun 06, 2016 at 05:16:45PM +0200, Igor Mammedov wrote:
> > > it will allow to drop custom cpu_x86_init() and use
> > > cpu_generic_init()
On 12 May 2016 at 23:46, Alistair Francis wrote:
> Add GPIO functionality to the register API. This allows association
> and automatic connection of GPIOs to bits in registers. GPIO inputs
> will attach to handlers that automatically set read-only bits in
> registers.
08.06.2016 04:11, Changlong Xie wrote:
> Block replication is a very important feature which is used for
> continuous checkpoints(for example: COLO).
...
I'm not sure I understand why this has been sent to qemu-trivial? :)
Thanks
/mjt
On 10 June 2016 at 14:25, Peter Maydell wrote:
> On 10 June 2016 at 12:48, Amit Shah wrote:
>>
>> The following changes since commit 0c33682d5f29b0a4ae53bdec4c8e52e4fae37b34:
>>
>> target-i386: Move user-mode exception actions out of user-exec.c
From: Aleksandar Markovic
Add preprocessor definition of FCR31's FS bit, and update related
code for setting this bit.
Signed-off-by: Aleksandar Markovic
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1
I referred to SoftFloat library in QEMU code, and the case "Operand is smaller
than INT_MIN" is different between SoftFloat and Mips-B, while the case
"Operand is a NaN" is different between SoftFloat and Mips-A.
Aleksandar
From: Maciej Rozycki
Sent:
From: Aleksandar Markovic
Updated handling of instructions .. Note that legacy
(pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore,
any NaN operand causes signaling invalid operation), while abs2008
ones are non-arithmetic, always
From: "Dr. David Alan Gilbert"
The discard code in migration/ram.c would send request for
zero length discards in the case where no discards were needed.
It doesn't appear to have had any bad effect.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by:
From: "Dr. David Alan Gilbert"
On the source, add a count of page requests received from the
destination.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Eric Blake
Reviewed-by: Denis V. Lunev
---
hmp.c
From: Andrea Arcangeli
I kept getting timeouts and unix socket accept failures under high
load, the patch fixes it.
Signed-off-by: Andrea Arcangeli
Reviewed-by: Marcel Apfelbaum
---
tests/libqtest.c | 2 +-
1 file changed, 1
On 8 June 2016 at 21:24, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> linux-user/strace.c | 25 ++---
> 1 file changed, 14 insertions(+), 11 deletions(-)
I think this change is correct, but it would be clearer to read
On 12 May 2016 at 23:46, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> QOMify registers as a child of TYPE_DEVICE. This allows registers to
> define GPIOs.
>
> Define an init helper that will do QOM initialisation.
You should
The code will be changed to allow creation of the CPU object and
report kvm_required errors only at realizefn, so we need to make
the instance_init function more flexible.
Signed-off-by: Eduardo Habkost
---
I am applying this before "Move xcc->kvm_required check to
realize
* Peter Maydell (peter.mayd...@linaro.org) wrote:
> On 10 June 2016 at 12:48, Amit Shah wrote:
> >
> > The following changes since commit 0c33682d5f29b0a4ae53bdec4c8e52e4fae37b34:
> >
> > target-i386: Move user-mode exception actions out of user-exec.c
> > (2016-06-09
From: Aleksandar Markovic
This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:
- Add fields that will keep FCR31's R/W bitmask in procesor
definitions and
From: Aleksandar Markovic
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added.
Reviewed-by: Leon Alrae
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by:
From: "Dr. David Alan Gilbert"
Knowing whether the destination host supports migration with
postcopy can be tricky.
The destination doesn't need the capability set, however
if we set it then use the opportunity to do the test and
tell the user/management layer early.
From: "Daniel P. Berrange"
Apply the following renames for starting incoming migration:
process_incoming_migration -> migration_fd_process_incoming
migration_set_incoming_channel -> migration_channel_process_incoming
migration_tls_set_incoming_channel ->
On Wed, Jun 08, 2016 at 01:30:11PM -0300, Eduardo Habkost wrote:
> On Mon, Jun 06, 2016 at 05:16:49PM +0200, Igor Mammedov wrote:
> > make SPARC target use sparc_cpu_parse_features() directly
> > so it won't get in the way of switching other propertified
> > targets to handling features as global
On Thu, Jun 09, 2016 at 07:11:00PM +0200, Igor Mammedov wrote:
> make SPARC target use sparc_cpu_parse_features() directly
> so it won't get in the way of switching other propertified
> targets to handling features as global properties.
>
> Signed-off-by: Igor Mammedov
On 12 May 2016 at 23:46, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> An API similar to the existing qdev_get_gpio_in() except gets outputs.
> Useful for:
>
> 1: Implementing lightweight devices that don't want to keep pointers
From: Aleksandar Markovic
v8 -> v9:
- patches 1 and 2 slightly reorganized to separate real changes from
cleanup changes more clearly
- unnecessary changes removed from patches 5 and 9
- changes related to FS bit moved to a separate patch (patch 10)
repository at:
git://git.kraxel.org/qemu tags/pull-ui-20160610-1
for you to fetch changes up to 1185fde40c3ba02406665b9ee0743270c526be26:
console: ignore ui_info updates which don't actually update something
(2016-06-10 11:16:18 +0200
On 10 June 2016 at 01:59, Andrew Jeffery wrote:
> On Thu, 2016-06-09 at 19:15 +0100, Peter Maydell wrote:
>> On 27 May 2016 at 06:08, Andrew Jeffery wrote:
>> >
>> > Value matching allows Linux to boot with CONFIG_NO_HZ_IDLE=y on the
>> > palmetto-bmc machine.
On Fri, 10 Jun 2016, Aleksandar Markovic wrote:
> I referred to SoftFloat library in QEMU code, and the case "Operand is
> smaller than INT_MIN" is different between SoftFloat and Mips-B, while
> the case "Operand is a NaN" is different between SoftFloat and Mips-A.
Ah, but then you just can
From: "Dr. David Alan Gilbert"
The RAM section of qmp_query_migrate is reasonably complex
and repeated 3 times. Split it out into a helper.
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: Eric Blake
Reviwed-by: Denis V. Lunev
From: "Dr. David Alan Gilbert"
Hi,
This is a small set of postcopy changes, the largest of which
is an x86 test for postcopy.
Andrea's libqtest change came about from running my test under very heavy
load.
The test includes a self contained migration workload that
On 8 June 2016 at 21:24, Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> linux-user/strace.c| 24
> linux-user/strace.list | 2 +-
> 2 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git
On 8 June 2016 at 21:24, Laurent Vivier wrote:
>int get_thread_area(struct user_desc *u_info);
>int set_thread_area(struct user_desc *u_info);
>
> Signed-off-by: Laurent Vivier
> ---
> linux-user/strace.list | 4 ++--
> 1 file changed, 2
On (Thu) 05 May 2016 [15:32:52], Liang Li wrote:
> At the end of live migration and before vm_start() on the destination
> side, we should make sure all the decompression tasks are finished, if
> this can not be guaranteed, the VM may get the incorrect memory data,
> or the updated memory may be
On Di, 2016-06-07 at 10:35 +0200, Olaf Hering wrote:
> On Mon, May 23, Gerd Hoffmann wrote:
>
> > +++ b/hw/usb/Makefile.objs
> > +common-obj-$(CONFIG_XEN_BACKEND) += xen-usb.o
> > +++ b/hw/usb/xen-usb.c
> > +usb_bus_new(>bus, sizeof(usbif->bus), _usb_bus_ops,
> > xen_sysdev);
>
> xen_sysdev
On 12 May 2016 at 23:46, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> Add a helper that will scan a static RegisterAccessInfo Array
> and populate a container MemoryRegion with registers as defined.
>
> Signed-off-by: Peter
On 12 May 2016 at 23:46, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> Define some macros that can be used for defining registers and fields.
>
> The REG32 macro will define A_FOO, for the byte address of a register
> as well as
From: "Dr. David Alan Gilbert"
Use the avx2 primitives during the test, thus making sure that the
compiler and assembler could actually use avx2.
This also detects the failure case on gcc 4.8.x with -save-temps
and avoids the need for the gcc version check in cutils.
From: "Dr. David Alan Gilbert"
When configured with --extra-cflags=-O2 gcc optimised out the test
and the readelf failed the check leaving avx2 disabled.
Signed-off-by: Dr. David Alan Gilbert
---
configure | 2 +-
1 file changed, 1 insertion(+), 1
From: "Dr. David Alan Gilbert"
Hi,
This pair of patches fixes a couple of issues that we found during test.
The first is that the configure test is pessimistic when compiled with -O2,
the second is that the explicit 4.9 gcc test is a bit coarse; I've removed
that test but
On 12 May 2016 at 23:46, Alistair Francis wrote:
> Add a minimal model for the devcfg device which is part of Zynq.
> This model supports DMA capabilities and interrupt generation.
>
> Signed-off-by: Peter Crosthwaite
> Signed-off-by:
On 12 May 2016 at 23:46, Alistair Francis wrote:
> From: Peter Crosthwaite
>
> Signed-off-by: Peter Crosthwaite
> Signed-off-by: Alistair Francis
> ---
> V4:
> - Small
From: Andrea Arcangeli
I kept getting timeouts and unix socket accept failures under high
load, the patch fixes it.
Signed-off-by: Andrea Arcangeli
Reviewed-by: Marcel Apfelbaum
Message-Id:
On Fri, Jun 10, 2016 at 5:21 PM, Sergey Fedorov wrote:
> On 26/05/16 19:35, Alvise Rigo wrote:
>> Using tcg_exclusive_{lock,unlock}(), make the emulation of
>> LoadLink/StoreConditional thread safe.
>>
>> During an LL access, this lock protects the load access itself, the
>>
On 10/06/16 18:53, alvise rigo wrote:
> On Fri, Jun 10, 2016 at 5:21 PM, Sergey Fedorov wrote:
>> On 26/05/16 19:35, Alvise Rigo wrote:
>>> Using tcg_exclusive_{lock,unlock}(), make the emulation of
>>> LoadLink/StoreConditional thread safe.
>>>
>>> During an LL access, this
We don't really want to go through the block layer in order to read from
or write to the vmstate in a qcow2 image. Doing so required a few ugly
hacks like saving and restoring the old image size (because writing to
vmstate offsets would increase the image size) or disabling the "reads
after EOF =
This series contains a few cleanups with respect to the vmstate I/O functions.
Apart from making the interface more consistent (writes were already vectored,
but not reads), this makes use of the new byte-based .bdrv_co_preadv/pwritev
callbacks in qcow2 to get rid of a few hacks, including
What if I combine both patches into single one?
10.06.2016, 19:33, "Peter Maydell" :
> On 10 June 2016 at 17:26, Sergey Sorokin wrote:
>> There are functions cpu_unaligned_access() and do_unaligned_access() that
>> are called with access type and
In QOM(QEMU Object Model) migrated objects are identified with instance_id
which is calculated automatically using their path in the QOM composition
tree. For some objects, this path could change from source to target in
migration. To migrate such objects, we need to make sure the instance_id does
Back in the 2.3.0 release we declared qcow[2] encryption as
deprecated, warning people that it would be removed in a future
release.
commit a1f688f4152e65260b94f37543521ceff8bfebe4
Author: Markus Armbruster
Date: Fri Mar 13 21:09:40 2015 +0100
block: Deprecate
This would require to fill again the whole history which I find very
unlikely. In any case, this has to be documented.
Thank you,
alvise
On Fri, Jun 10, 2016 at 6:00 PM, Sergey Fedorov wrote:
> On 10/06/16 18:53, alvise rigo wrote:
>> On Fri, Jun 10, 2016 at 5:21 PM,
The return value of .bdrv_load/save_vmstate() can be any non-negative
number in case of success now. It used to be bytes/-errno.
Signed-off-by: Kevin Wolf
---
block/io.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/block/io.c
Use ldl_le_p() and stl_le_p() instead of le32_to_cpup() and
cpu_to_le32w(); the former handle misaligned addresses and don't
need casts, and the latter are deprecated.
Signed-off-by: Peter Maydell
---
hw/sh4/sh_pci.c | 4 ++--
1 file changed, 2 insertions(+), 2
Currently we cannot directly transfer a QTAILQ instance because of the
limitation in the migration code. Here we introduce an approach to
transfer such structures. In our approach such a structure is tagged
with VMS_LINKED. We then modified vmstate_save_state and vmstate_load_state
so that when
c.c
> (2016-06-09 15:55:02 +0100)
>
> are available in the git repository at:
>
> git://github.com/rth7680/qemu.git tags/pull-tcg-20160610
>
> for you to fetch changes up to 9b1b8e78a5a8c849f5ca800d71497dc88a338483:
>
> translate-all: add tb hash
Sergey Fedorov writes:
> On 26/05/16 19:35, Alvise Rigo wrote:
>> Using tcg_exclusive_{lock,unlock}(), make the emulation of
>> LoadLink/StoreConditional thread safe.
>>
>> During an LL access, this lock protects the load access itself, the
>> update of the exclusive
On Fri, Jun 10, 2016 at 16:33:10 +0100, Peter Maydell wrote:
> Fails to build on ppc64be :-(
>
> In file included from /home/pm215/qemu/include/qemu/thread.h:4:0,
> from /home/pm215/qemu/include/block/aio.h:20,
> from /home/pm215/qemu/include/block/block.h:4,
>
v4: - Introduce a way to set customized instance_id in SaveStateEntry. Use it
to set instance_id for DRC using its unique index to address David
Gibson's concern.
- Rename VMS_CSTM to VMS_LINKED based on Paolo Bonzini's suggestions.
- Clean up qjson stuff in put_qtailq.
-
On Tue, Jun 07, 2016 at 07:30:19PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 03.06.2016 18:45, Denis V. Lunev wrote:
> > On 06/03/2016 06:06 PM, Eric Blake wrote:
> > > On 06/03/2016 08:05 AM, Vladimir Sementsov-Ogievskiy wrote:
> > > > Add target-zeroed flag to allow user specify that
The changes that make QEMU behavior the same as hardware behavior (in relation
to CEIL, CVT, FLOOR, ROUND, TRUNC Mips instructions) are already contained in
this patch.
I just mentioned Mips-A / Mips-B / SoftFloat differences as an
explanation/observation related to the change in this patch.
It is always true for open images now.
Signed-off-by: Kevin Wolf
---
block.c | 2 --
block/io.c| 51 +--
include/block/block_int.h | 3 ---
3 files changed, 23 insertions(+), 33 deletions(-)
diff
The cpu_to_*w() functions just compose a pointer dereference
with a byteswap. Instead use st*_p(), which handles potential
pointer misalignment and avoids the need to cast the pointer.
Signed-off-by: Peter Maydell
---
nbd/client.c | 10 +-
1 file changed, 5
On Thu, Jun 09, 2016 at 04:17:11PM +0200, Lluís Vilanova wrote:
> >> @@ -61,7 +69,7 @@ static inline bool
> >> trace_event_get_state_static(TraceEvent *ev)
> >> static inline bool trace_event_get_state_dynamic_by_id(TraceEventID id)
> >> {
> >> /* it's on fast path, avoid consistency checks
On 10 June 2016 at 17:26, Sergey Sorokin wrote:
> There are functions cpu_unaligned_access() and do_unaligned_access() that
> are called with access type and mmu index arguments. But these arguments
> are named 'is_write' and 'is_user' in their declarations.
> The patch fixes
On 10 June 2016 at 17:42, Sergey Sorokin wrote:
> What if I combine both patches into single one?
No particular objection.
-- PMM
To manage hotplug/unplug of dynamic resources such as PCI cards,
memory, and CPU on sPAPR guests, a firmware abstraction known as
a Dynamic Resource Connector (DRC) is used to assign a particular
dynamic resource to the guest, and provide an interface for the
guest to manage configuration/removal
Use stl_le_p() and ldl_le_p() to read and write data from
buffers, rather than using pointer casts and cpu_to_le32()
for writes and le32_to_cpup() for reads. This:
* avoids lots of casts
* works even if the buffer isn't as aligned as the host would like
* avoids using the *_to_cpup() functions
There are functions tlb_fill(), cpu_unaligned_access() and
do_unaligned_access() that are called with access type and mmu index
arguments. But these arguments are named 'is_write' and 'is_user' in their
declarations. The patches fix the names to avoid a confusion.
Sergey Sorokin (2):
Fix
The function tlb_fill() is called with access type argument which is named
'is_write' in its declaration. The patch fixes the argument name
to avoid a confusion.
Signed-off-by: Sergey Sorokin
---
include/exec/exec-all.h | 2 +-
target-alpha/mem_helper.c | 4 ++--
I agree
10.06.2016, 19:33, "Peter Maydell" :
> On 10 June 2016 at 17:26, Sergey Sorokin wrote:
>> There are functions cpu_unaligned_access() and do_unaligned_access() that
>> are called with access type and mmu index arguments. But these arguments
Current migration code cannot handle some data structures such as
QTAILQ in qemu/queue.h. Here we extend the signatures of put/get
in VMStateInfo so that customized handling is supported.
Signed-off-by: Jianjun Duan
---
hw/net/vmxnet3.c| 18 ++---
ccs_list in spapr state maintains the device tree related
information on the rtas side for hotplugged devices. In racing
situations between hotplug events and migration operation, a rtas
hotplug event could be migrated from the source guest to target
guest, or the source guest could have not yet
In racing situations between hotplug events and migration operation,
a rtas hotplug event could have not yet be delivered to the source
guest when migration is started. In this case the pending_events of
spapr state need be transmitted to the target so that the hotplug
event can be finished on the
cpu-common.h is not included in qom/cpu.h
what do you think? Should it be included? Or may be MMUAccessType should be
just moved into another header. For example into exec/memattrs.h
10.06.2016, 19:44, "Peter Maydell" :
> On 10 June 2016 at 17:42, Sergey Sorokin
682d5f29b0a4ae53bdec4c8e52e4fae37b34:
>>
>> target-i386: Move user-mode exception actions out of user-exec.c
>> (2016-06-09 15:55:02 +0100)
>>
>> are available in the git repository at:
>>
>> git://github.com/rth7680/qemu.git tags/pull-tcg-20160610
>&g
This allows drivers to share code between normal I/O and vmstate
accesses.
Signed-off-by: Kevin Wolf
---
block/io.c| 80 ++-
include/block/block_int.h | 10 +++---
2 files changed, 64 insertions(+), 26 deletions(-)
This brings it in line with .bdrv_save_vmstate().
Signed-off-by: Kevin Wolf
---
block/io.c| 26 +-
block/qcow2.c | 6 +++---
block/sheepdog.c | 13 ++---
include/block/block.h | 1 +
There are functions cpu_unaligned_access() and do_unaligned_access() that
are called with access type and mmu index arguments. But these arguments
are named 'is_write' and 'is_user' in their declarations.
The patch fixes the names to avoid a confusion.
Signed-off-by: Sergey Sorokin
Use the name 'cpus' instead of 'smp_cpus' to be consistent with
MachineState.cpus. This also makes grepping for the global
smp_cpus easier.
Signed-off-by: Andrew Jones
---
hw/arm/virt-acpi-build.c | 14 +++---
hw/arm/virt.c| 14
This is a first step to preparing mach-virt for configurable
cpu topology, and is necessary now to prepare to move smbios
code away from using cpu topology globals smp_cores,smp_threads.
Signed-off-by: Andrew Jones
---
hw/arm/virt.c| 6 +-
This series is a first step in eliminating smp_* global
variables (the last patch gets rid of two of them!) And, it's
a first step in deprecating '-smp' in favor of using machine
properties, e.g.
qemu -machine pc,sockets=2,cores=2,threads=2,maxcpus=8,cpus=8 ...
It's also a first step in allowing
SMBIOS needs cpu topology for Type4 tables, so we need to pass
it in. There are several parameters so we use a structure. There
are two callers (of non-legacy, which generates Type4 tables),
x86 and arm, so we also update both to pass the topology
parameters from their MachineState properties
Signed-off-by: Andrew Jones
---
hw/core/machine.c | 81 +
include/hw/boards.h | 6
2 files changed, 87 insertions(+)
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 3dce9020e510a..2625044002e57 100644
---
Use CPUState nr_cores,nr_threads and MachineState
cores,threads instead.
Signed-off-by: Andrew Jones
---
hw/ppc/spapr.c | 9 +
hw/ppc/spapr_rtas.c | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index
On 06/10/2016 10:09 AM, Peter Maydell wrote:
> The *_to_cpup() and cpu_to_*w() functions just compose a pointer
> dereference with a byteswap. Instead use ld*_p() and st*_p(),
> which handle potential pointer misalignment and avoid the need
> to cast the pointer.
>
> Signed-off-by: Peter Maydell
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Signed-off-by: Andrew Jones
---
hw/core/machine.c | 6 ++
include/hw/boards.h | 1 +
vl.c| 1 +
3 files changed, 8 insertions(+)
diff --git a/hw/core/machine.c
Stefan Hajnoczi writes:
> On Thu, Jun 09, 2016 at 04:17:11PM +0200, Lluís Vilanova wrote:
>> >> @@ -61,7 +69,7 @@ static inline bool
>> >> trace_event_get_state_static(TraceEvent *ev)
>> >> static inline bool trace_event_get_state_dynamic_by_id(TraceEventID id)
>> >> {
>> >> /* it's on fast
Move the guts of smp_parse() into hw/core/machine.c to operate on
smp machine properties, and to eventually allow it to be overridden
by machines. We leave the smp_parse function behind to handle the
(now deprecated) -smp option, but now it only needs to set the
machine properties.
Signed-off-by:
Use CPUState nr_threads instead.
Signed-off-by: Andrew Jones
---
target-ppc/translate_init.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index a1db5009c4a83..f442b2fc934d1
This ensures that the underlying memory is marked dirty once the transfer
is complete and resolves cache coherency problems under MacOS 9.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c | 46 +---
change_parent_backing_link() asserts that the BDS to be replaced is not
used as a backing file. However, we may want to replace a BDS by its
overlay in which case that very link should not be redirected.
For instance, when doing a sync=none drive-mirror operation, we may have
the following BDS/BB
Issue #1: If the target image does not have a backing BDS before mirror
completion, qemu tries really hard to give it a backing BDS. If the
source has a backing BDS, it will actually always "succeed".
In some cases, the target is not supposed to have a backing BDS, though
(absolute-paths: because
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