Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation

David Gibson writes: > On Wed, Sep 07, 2016 at 08:13:31AM +0100, Alex Bennée wrote: >> >> David Gibson writes: >> >> > On Wed, Sep 07, 2016 at 10:17:42AM +0530, Nikunj A Dadhania wrote: >> >> David Gibson

Re: [Qemu-devel] [PATCH] virtio-bus: Plug devices after features are negotiated

On Sat, 10 Sep 2016 10:23:37 +0200 Maxime Coquelin wrote: > Currently, devices are plugged before features are negotiated. > If the backend doesn't support VIRTIO_F_VERSION_1, the transport > need to rewind some settings. > > This is the case for CCW, for which a

[Qemu-devel] [PATCH v6 08/18] qapi: export the marshallers

Make it possible to call marshallers manually, without going through qmp_dispatch(). (this is currently only possible in middle-mode, but it's also useful in general) Signed-off-by: Marc-André Lureau --- scripts/qapi-commands.py | 8 ++-- 1 file changed, 2

[Qemu-devel] [PATCH v6 14/18] tests: add a test to check invalid args

Check that invalid args on commands without arguments returns an error. Signed-off-by: Marc-André Lureau --- tests/test-qga.c | 21 + 1 file changed, 21 insertions(+) diff --git a/tests/test-qga.c b/tests/test-qga.c index 21f44f8..40af649 100644

[Qemu-devel] [v4 1/6] hw/msi: Allow platform devices to use explicit SID

When using IOMMU platform devices like IOAPIC are required to make interrupt remapping requests using explicit SID.We affiliate an MSI route with a requester ID and a PCI device if present which ensures that platform devices can call IOMMU interrupt remapping code with explicit SID while

[Qemu-devel] [v4 4/6] hw/iommu: AMD IOMMU interrupt remapping

Introduce AMD IOMMU interrupt remapping and hook it onto the existing interrupt remapping infrastructure Signed-off-by: David Kiarie --- hw/i386/amd_iommu.c | 240 +++- hw/i386/amd_iommu.h | 4 +- hw/intc/ioapic.c|

[Qemu-devel] [PATCH v6 02/18] qapi-schema: use generated marshaller for 'qmp_capabilities'

qapi'fy the 'qmp_capabilities' command, makes the command visible in query-qmp-schema. Signed-off-by: Marc-André Lureau Reviewed-by: Eric Blake Reviewed-by: Markus Armbruster --- monitor.c| 4 ++-- qapi-schema.json |

[Qemu-devel] [PATCH v6 00/18] qapi: remove the 'middle' mode

Hi, Although some QMP commands are still not fully qapi'fied, it is possible to use more qapi common and generated code by dropping the 'middle' mode and use qmp_dispatch(). v6: - get back to v4 approach, and unregister commands at run-time. (Markus Armbruster) - comments and commit messages

Re: [Qemu-devel] [PATCH] virtio-bus: Plug devices after features are negotiated

On 09/12/2016 10:51 AM, Cornelia Huck wrote: On Sat, 10 Sep 2016 10:23:37 +0200 Maxime Coquelin wrote: Currently, devices are plugged before features are negotiated. If the backend doesn't support VIRTIO_F_VERSION_1, the transport need to rewind some settings.

[Qemu-devel] [PATCH v6 03/18] qapi-schema: add 'device_add'

Even though device_add is not fully qapi'fied, we may add it to the json schema with 'gen': false, so registration and documentation can be generated. Signed-off-by: Marc-André Lureau Reviewed-by: Eric Blake --- qapi-schema.json | 40

[Qemu-devel] [PATCH v6 01/18] build-sys: define QEMU_VERSION_{MAJOR, MINOR, MICRO}

There are better chances to find what went wrong at build time than a later assert in qmp_query_version Signed-off-by: Marc-André Lureau --- qmp.c | 16 +++- scripts/create_config | 6 ++ 2 files changed, 9 insertions(+), 13

[Qemu-devel] [PATCH v6 04/18] monitor: simplify invalid_qmp_mode()

handle_qmp_command() will switch to use qmp_dispatch(). It won't have a pointer to the marshaller function anymore, but only the name of the command to invoke. Simplify invalid_qmp_mode() so it can just be called with the command name. Signed-off-by: Marc-André Lureau

[Qemu-devel] [PATCH v6 05/18] monitor: register gen:false commands manually

Since a few commands are using 'gen': false, they are not registered automatically by the generator. Register manually instead. This is in preparation for removal of qapi 'middle' mode generation. Note that qmp_init_marshal() function isn't run yet, so the commands aren't actually registered,

[Qemu-devel] [PATCH v6 06/18] qapi: Support unregistering QMP commands

From: Markus Armbruster Signed-off-by: Markus Armbruster Reviewed-by: Marc-André Lureau --- qapi/qmp-registry.c | 8 include/qapi/qmp/dispatch.h | 1 + 2 files changed, 9 insertions(+) diff --git

[Qemu-devel] [PATCH v6 16/18] build-sys: remove qmp-commands-old.h

Signed-off-by: Marc-André Lureau Reviewed-by: Eric Blake --- Makefile.target | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/Makefile.target b/Makefile.target index 8c7a072..19cc49c 100644 --- a/Makefile.target +++

[Qemu-devel] [PATCH v6 07/18] qmp: Hack to keep commands configuration-specific

We currently define QMP commands in two places: the QAPI schema and qmp-commands.hx. The latter is preprocessed, the former is not. We use the preprocessor to suppress configuration-specific commands. For instance, query-spice is only available #ifdef CONFIG_SPICE. QMP command dispatch and

[Qemu-devel] [PATCH v6 13/18] qapi: check invalid arguments on no-args commands

The generated marshal functions do not visit arguments from commands that take no arguments. Thus they fail to catch invalid members. Visit the arguments, if provided, to throw an error in case of invalid members. Currently, qmp_check_client_args() checks for invalid arguments and correctly

Re: [Qemu-devel] [PATCH 2/3] virtio: add virtqueue_rewind()

On Thu, Sep 08, 2016 at 09:30:13AM +0200, Ladi Prosek wrote: > On Thu, Sep 8, 2016 at 8:44 AM, Roman Kagan wrote: > > On Wed, Sep 07, 2016 at 05:20:48PM +0200, Ladi Prosek wrote: > >> From: Stefan Hajnoczi > >> > >> virtqueue_discard() requires a

[Qemu-devel] [PATCH v6 15/18] monitor: use qmp_dispatch()

Replace the old manual dispatch and validation code by the generic one provided by qapi common code. Note that it is now possible to call the following commands that used to be disabled by compile-time conditionals: - dump-skeys - query-spice - rtc-reset-reinjection - query-gic-capabilities

[Qemu-devel] [PATCHv2 1/8] tests: cris: force inlining

From: Rabin Vincent The CRIS tests expect that functions marked inline are always inline. With newer versions of GCC, building them results warnings like the following and spurious failures when they are run. In file included from tests/tcg/cris/check_moveq.c:5:0:

[Qemu-devel] [v4 5/6] hw/acpi: report IOAPIC on IVRS

Report IOAPIC via IVRS which effectively allows linux AMD-Vi driver to enable interrupt remapping Signed-off-by: David Kiarie --- hw/i386/acpi-build.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index c20bc71..c9bee8f

[Qemu-devel] [PATCH v6 09/18] monitor: use qmp_find_command() (using generated qapi code)

Stop using the so-called 'middle' mode. Instead, use qmp_find_command() from generated qapi commands registry. Update and fix the documentation too. Signed-off-by: Marc-André Lureau --- monitor.c | 14 ++-- vl.c | 1 +

[Qemu-devel] [PATCH v6 10/18] monitor: implement 'qmp_query_commands' without qmp_cmds

One step towards getting rid of the static qmp_cmds table. Signed-off-by: Marc-André Lureau Reviewed-by: Eric Blake --- monitor.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/monitor.c

[Qemu-devel] [PATCH v6 11/18] monitor: remove mhandler.cmd_new

This is no longer necessary now that we aren't using middle mode anymore. Signed-off-by: Marc-André Lureau Reviewed-by: Eric Blake --- monitor.c | 13 +-- docs/writing-qmp-commands.txt | 4 +- hmp-commands-info.hx

[Qemu-devel] issues about igd-passthrough using vfio-pci

Hello， I have realized the IGD passthrough with Intel(R) Core(TM) i7-4770 CPU，but when I change the platform with the Intel Core i3-6100U，it doesn’t have any VGA output and windows7 refuses to boot with black screen. This problem has been bothering me for a long time,someone can help me?

[Qemu-devel] [PATCH v6 12/18] qapi: remove the "middle" mode

Now that the register function is always generated, we can remove the so-called "middle" mode from the generator script. Signed-off-by: Marc-André Lureau --- scripts/qapi-commands.py | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git

Re: [Qemu-devel] KVM call for agenda for 2016-09-13

Juan Quintela wrote: > Hi > > Please, send any topic that you are interested in covering. > > At the end of Monday I will send an email with the agenda or the > cancellation of the call, so hurry up. Hi Kindly remind if you have any topic for Tomorrow. Thanks, Juan. > >

Re: [Qemu-devel] [PATCH v3 0/3] ppc: Broadcast tlb flush should have global effect

On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: > PowerPC targets should do tlb invalidation on other cpus on  > instructions that expect a global effect. > > * ptesync for BookS > * tlbsync primarily for BookE >   (for BookS make it a nop, as it always come along with ptesync) > *

[Qemu-devel] [PATCH v2] kvm-all: drop kvm_setup_guest_memory

kvm_setup_guest_memory only does "madvise to QEMU_MADV_DONTFORK" and is only called by ram_block_add, which actually is duplicate code. Bonus: add simple comment for kvm_has_sync_mmu to make life easier. Suggested-by: Paolo Bonzini Signed-off-by: Cao jin

[Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro

Use macro for ld64 as well, this changes the function signature from gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 39 +++---

[Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro

Use macro for ld64 as well, this changes the function signature from gen_qemu_st64 => gen_qemu_st64_i64. Replace this at all the call sites. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 37 ++--

[Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x

stxvb16x: Store VSX Vector Byte*16 stxvh8x: Store VSX Vector Halfword*8 Signed-off-by: Nikunj A Dadhania --- target-ppc/translate/vsx-impl.inc.c | 55 + target-ppc/translate/vsx-ops.inc.c | 2 ++ 2 files changed, 57 insertions(+)

Re: [Qemu-devel] [PATCH v2 0/8] nvdimm: hotplug support

On 08/12/2016 11:13 PM, Igor Mammedov wrote: Reviewed-by: Stefan Hajnoczi I'd like to review it but I need to read NVDIMM/ACPI specs first to make sensible comments. However it will take some time and I'm on vacation starting next week and I'll be back in a month. So

Re: [Qemu-devel] [PATCH v3 13/34] tcg: Add atomic helpers

On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote: > On 09/09/2016 07:46 AM, Leon Alrae wrote: > >Wouldn't it be useful if tcg.h provided also aliases for _le/_be atomic > >helpers (equivalent to helper_ret_X_mmu) so that in target-* code we wouldn't > >need to care about the

Re: [Qemu-devel] [Qemu-ppc] [PATCH v4 2/3] tests: make pc_alloc_init/init_flags/uninit generic

On Mon, 12 Sep 2016 11:27:57 +1000 David Gibson wrote: > On Fri, Sep 09, 2016 at 02:31:55PM +0200, Laurent Vivier wrote: > > > > > > On 09/09/2016 14:25, Greg Kurz wrote: > > > On Thu, 8 Sep 2016 09:50:31 +0200 > > > Laurent Vivier wrote: > >

Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation

On Mon, 2016-09-12 at 09:39 +0100, Alex Bennée wrote: >  > They are now in Richard's tcg-next queue > > Message-Id: <1473282648-23487-1-git-send-email-...@twiddle.net> > Subject: [Qemu-devel] [PULL 00/18] tcg queued patches > > All the backends support the new fence op, so far only ARM, Alpha

[Qemu-devel] [PATCH v6 18/18] Replace qmp-commands.hx by docs/qmp-commands.txt

The only remaining function of qmp-commands.hx is to let us generate qmp-commands.txt from it. Replace qmp-commands.hx by qmp-commands.txt. We intend to move the documentation into the QAPI schema and generate qapi-commands.txt from it, but not right now. Signed-off-by: Marc-André Lureau

[Qemu-devel] [PATCH v6 17/18] qmp-commands.hx: fix some styling

Add some missing lines, remove superflous @ in command name, remove trailing spaces. Signed-off-by: Marc-André Lureau --- qmp-commands.hx | 34 ++ 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/qmp-commands.hx

[Qemu-devel] [v4 2/6] hw/i386: enforce SID verification

Platform devices are now able to make interrupt request with explicit SIDs hence we can safely expect triggered AddressSpace ID to match the requesting ID Signed-off-by: David Kiarie --- hw/i386/intel_iommu.c | 77 ++- 1

[Qemu-devel] [v4 3/6] hw/iommu: Prepare for AMD IOMMU interrupt remapping

Introduce macros and trace events for use in AMD IOMMU interrupt remapping Signed-off-by: David Kiarie --- hw/i386/amd_iommu.h | 80 hw/i386/trace-events | 7 + 2 files changed, 87 insertions(+) diff --git

[Qemu-devel] [v4 6/6] hw/iommu: share common code between IOMMUs

Enabling interrupt remapping with kernel_irqchip=on should result in an error for both VT-d and AMD-Vi Signed-off-by: David Kiarie --- hw/i386/intel_iommu.c | 9 - hw/i386/x86-iommu.c | 8 2 files changed, 8 insertions(+), 9 deletions(-) diff --git

[Qemu-devel] [v4 0/6] AMD IOMMU Interrupt remapping

Hello, This patchset adds AMD IOMMU interrupt remapping logic to Qemu. I have made some changes to the way X86 Qemu manages MSI routes. The current code assumes that MSI routes are affiliated to a PCI device which will not always be the case with split irqchip. With split irqchip platform

[Qemu-devel] [Bug 1622547] [NEW] qemu-system-sparc fatal error Trap 0x29 on Solaris 2.6

Public bug reported: When trying to install Solaris 2.6 from original CDROM, qemu fail with the following error : qemu: fatal: Trap 0x29 while interrupts disabled, Error state pc: f0041280 npc: f0041284 %g0-7: f0281800 0800 f0243b88 0001 f0244020 %o0-7:

[Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4

1) Consolidate Load/Store operations using tcg_gen_qemu_ld/st functions 2) This series contains 10 new instructions for POWER9 ISA3.0 Use newer qemu load/store tcg helpers and optimize stxvw4x and lxvw4x. Patches: 01-09: Cleanup load/store operations in ppc translator 10: xxspltib: VSX

[Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur to use new macro

Make byte-swap routines use the common GEN_QEMU_LOAD macro Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 27 ++- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c

[Qemu-devel] [PATCH RESEND v2 07/17] target-ppc: consolidate load with reservation

Use tcg_gen_qemu_ld in the load with reservation instructions. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c

[Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional

Use tcg_gen_qemu_st store conditional instructions. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 58 +- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/target-ppc/translate.c

[Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction

xxspltib: VSX Vector Splat Immediate Byte Copy the immediate byte in each byte of target VSR Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 2 ++ target-ppc/translate/vsx-impl.inc.c | 20

[Qemu-devel] [PATCH RESEND v2 15/17] target-ppc: add lxvb16x and lxvh8x

lxvb16x: Load VSX Vector Byte*16 lxvh8x: Load VSX Vector Halfword*8 Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 1 + target-ppc/mem_helper.c | 6 target-ppc/translate/vsx-impl.inc.c | 57

[Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction

From: Ravi Bangoria darn: Deliver A Random Number Currently return invalid random number for all the case. This needs proper algorithm to provide cryptographically suitable random data. Reading from /dev/random can block and that is not an expected behaviour

Re: [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4

Hi, Your series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1473662506-27441-1-git-send-email-nik...@linux.vnet.ibm.com Subject: [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4 === TEST SCRIPT BEGIN ===

Re: [Qemu-devel] [PATCH v3 0/3] ppc: Broadcast tlb flush should have global effect

Benjamin Herrenschmidt writes: > On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: >> PowerPC targets should do tlb invalidation on other cpus on  >> instructions that expect a global effect. >> >> * ptesync for BookS >> * tlbsync primarily for BookE >>  

Re: [Qemu-devel] [PATCH] kvm-all: drop kvm_setup_guest_memory

Hi, Your series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Type: series Message-id: 1473591360-13163-1-git-send-email-caoj.f...@cn.fujitsu.com Subject: [Qemu-devel] [PATCH] kvm-all:

Re: [Qemu-devel] [PATCH 2/2] vhost-user: only seek a reply if needed in set_mem_table

On 09/08/2016 05:15 PM, Michael S. Tsirkin wrote: On Thu, Sep 08, 2016 at 10:34:10AM +0200, Maxime Coquelin wrote: The goal of this patch is to only request a sync (reply_ack, or get_features) in set_mem_table only when necessary. It should not be necessary the first time we set the table,

[Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations

Implement macro to consolidate store operations using newer tcg_gen_qemu_st function. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git

[Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation

Manipulate data and store 8bytes instead of 4bytes. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate/vsx-impl.inc.c | 27 +-- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target-ppc/translate/vsx-impl.inc.c

Re: [Qemu-devel] [PATCH v7 1/4] vfio: Mediated device Core driver

On 9/12/2016 10:40 AM, Jike Song wrote: > On 09/10/2016 03:55 AM, Kirti Wankhede wrote: >> On 9/10/2016 12:12 AM, Alex Williamson wrote: >>> On Fri, 9 Sep 2016 23:18:45 +0530 >>> Kirti Wankhede wrote: >>> On 9/8/2016 1:39 PM, Jike Song wrote: > On 08/25/2016 11:53

Re: [Qemu-devel] [PATCH v2] qom: Implement qom-get HMP command

"Daniel P. Berrange" writes: > On Fri, Sep 09, 2016 at 06:21:15PM +0200, Markus Armbruster wrote: >> "Dr. David Alan Gilbert" writes: >> >> > * Daniel P. Berrange (berra...@redhat.com) wrote: >> >> IIUC, you switched because string-output-visitor could

Re: [Qemu-devel] [PATCH v3 3/3] target-ppc: tlbie should have global effect

Benjamin Herrenschmidt writes: > On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 5026804..d96ff66 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -4448,6

[Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction

stxsibx - Store VSX Scalar as Integer Byte Indexed stxsihx - Store VSX Scalar as Integer Halfword Indexed Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 2 ++ target-ppc/translate/vsx-impl.inc.c | 3 +++ target-ppc/translate/vsx-ops.inc.c

[Qemu-devel] [PATCH RESEND v2 14/17] target-ppc: improve lxvw4x implementation

Load 8byte at a time and manipulate. Signed-off-by: Nikunj A Dadhania --- target-ppc/helper.h | 1 + target-ppc/mem_helper.c | 5 + target-ppc/translate/vsx-impl.inc.c | 34 -- 3 files changed, 26

Re: [Qemu-devel] [PATCH v3 3/3] target-ppc: tlbie should have global effect

On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 5026804..d96ff66 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -4448,6 +4448,7 @@ static void gen_tlbie(DisasContext *ctx) >  #if

[Qemu-devel] [PATCH RESEND v2 12/17] target-ppc: add lxsi[bw]zx instruction

lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 2 ++ target-ppc/translate/vsx-impl.inc.c | 2 ++

Re: [Qemu-devel] [PATCH] virtio-gpu-pci: tag as not hotpluggable

On Fr, 2016-09-09 at 21:16 +0300, Michael S. Tsirkin wrote: > On Thu, Sep 08, 2016 at 09:17:17AM +0200, Gerd Hoffmann wrote: > > We can't hotplug display adapters in qemu, tag virtio-gpu-pci > > accordingly (virtio-vga already has this). > > > > Signed-off-by: Gerd Hoffmann >

Re: [Qemu-devel] [PATCH v4 0/4] Introduce error_report_{fatal|abort}

"Daniel P. Berrange" writes: > On Fri, Sep 09, 2016 at 07:05:04PM +0200, Markus Armbruster wrote: >> Peter Xu writes: >> >> > v4 changes: >> > - remove two standard headers since they are included in osdep.h >> > already [Fam] >> > - make sure it

Re: [Qemu-devel] [PATCH v3 3/3] target-ppc: tlbie should have global effect

Benjamin Herrenschmidt writes: > On Mon, 2016-09-12 at 11:18 +0530, Nikunj A Dadhania wrote: >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >> index 5026804..d96ff66 100644 >> --- a/target-ppc/translate.c >> +++ b/target-ppc/translate.c >> @@ -4448,6

[Qemu-devel] [PATCH RESEND v2 01/17] target-ppc: consolidate load operations

Implement macro to consolidate store operations using newer tcg_gen_qemu_ld functions. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 58 +- 1 file changed, 20 insertions(+), 38 deletions(-) diff --git

[Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r to use new macro

Make byte-swap routines use the common GEN_QEMU_LOAD macro Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 32 ++-- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/target-ppc/translate.c

[Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation

Being a 16byte operation, qemu_ld/st still does not support this. Move this out so other store operation can use qemu_ld/st in the following patch. Also, convert it to two MO_Q operations for stqcx. Signed-off-by: Nikunj A Dadhania --- target-ppc/translate.c | 69

[Qemu-devel] [PATCH v1] spapr: Introduce sPAPRCPUCoreClass

Each spapr cpu core type defines an instance_init routine which just populates the CPU class name. This can be done in the class_init commonly for all core types which simplifies the registration. This is inspired by how PowerNV core types are registered. Certain types of spapr cpu cores ('host'

[Qemu-devel] [PATCH v7 00/16] cpu-exec: Safe work in quiescent state

In addition to fixing some of the issues found by Alex, safe work items need not run anymore with a mutex taken. Of course, cpu_exec_start/end and start_exclusive/end_exclusive are essentially the read and write side of a specialized rwlock, so there is still a lock in disguise looming to cause

[Qemu-devel] [PATCH 08/16] cpus-common: fix uninitialized variable use in run_on_cpu

Signed-off-by: Paolo Bonzini --- cpus-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpus-common.c b/cpus-common.c index b98f548..cdfdb14 100644 --- a/cpus-common.c +++ b/cpus-common.c @@ -88,8 +88,7 @@ struct qemu_work_item { struct

[Qemu-devel] [PATCH 04/16] linux-user: Use QemuMutex and QemuCond

From: Sergey Fedorov Convert pthread_mutex_t and pthread_cond_t to QemuMutex and QemuCond. This will allow to make some locks and conditional variables common between user and system mode emulation. Signed-off-by: Sergey Fedorov Signed-off-by: Sergey

[Qemu-devel] [PATCH 03/16] cpus: Rename flush_queued_work()

From: Sergey Fedorov To avoid possible confusion, rename flush_queued_work() to process_queued_cpu_work(). Signed-off-by: Sergey Fedorov Signed-off-by: Sergey Fedorov Reviewed-by: Alex Bennée

[Qemu-devel] [PATCH 01/16] cpus: pass CPUState to run_on_cpu helpers

From: Alex Bennée CPUState is a fairly common pointer to pass to these helpers. This means if you need other arguments for the async_run_on_cpu case you end up having to do a g_malloc to stuff additional data into the routine. For the current users this isn't a massive

[Qemu-devel] [PATCH 13/16] cpus-common: simplify locking for start_exclusive/end_exclusive

It is not necessary to hold qemu_cpu_list_mutex throughout the exclusive section, because no other exclusive section can run while pending_cpus != 0. exclusive_idle() is called in cpu_exec_start(), and that prevents any CPUs created after start_exclusive() from entering cpu_exec() during an

[Qemu-devel] [PATCH 07/16] cpus-common: move CPU work item management to common code

From: Sergey Fedorov Make CPU work core functions common between system and user-mode emulation. User-mode does not use run_on_cpu, so do not implement it. Signed-off-by: Sergey Fedorov Signed-off-by: Sergey Fedorov

Re: [Qemu-devel] [v4 4/6] hw/iommu: AMD IOMMU interrupt remapping

On Mon, Sep 12, 2016 at 01:08:07PM +0300, David Kiarie wrote: [...] > /* configure MMIO registers at startup/reset */ > static void amdvi_set_quad(AMDVIState *s, hwaddr addr, uint64_t val, > uint64_t romask, uint64_t w1cmask) > @@ -641,6 +667,11 @@ static void

Re: [Qemu-devel] [v4 4/6] hw/iommu: AMD IOMMU interrupt remapping

On Mon, Sep 12, 2016 at 02:51:27PM +0300, David Kiarie wrote: > On Mon, Sep 12, 2016 at 2:34 PM, Peter Xu wrote: > > > On Mon, Sep 12, 2016 at 01:08:07PM +0300, David Kiarie wrote: > > > > [...] > > > > > /* configure MMIO registers at startup/reset */ > > > static void

Re: [Qemu-devel] [PATCH v2 0/8] nvdimm: hotplug support

On Mon, 12 Sep 2016 15:33:53 +0800 Xiao Guangrong wrote: > On 08/12/2016 11:13 PM, Igor Mammedov wrote: > > >> > >> Reviewed-by: Stefan Hajnoczi > > I'd like to review it but I need to read NVDIMM/ACPI specs first > > to make sensible

[Qemu-devel] [PATCH 5/5] QMP: fixup typos and whitespace damage

From: Christian Borntraeger Fixup some typos and whitespace damage introduced by the CPU model patches for s390. Reported-by: Eric Blake Signed-off-by: Christian Borntraeger Signed-off-by: Cornelia Huck

[Qemu-devel] [PATCH 3/5] virtio-ccw: respond to READ_STATUS command

From: Pierre Morel This patch adds the response to the READ_STATUS CCW command. Signed-off-by: Pierre Morel Signed-off-by: Cornelia Huck --- hw/s390x/virtio-ccw.c | 20 hw/s390x/virtio-ccw.h

Re: [Qemu-devel] [v4 1/6] hw/msi: Allow platform devices to use explicit SID

On Mon, Sep 12, 2016 at 01:08:04PM +0300, David Kiarie wrote: > When using IOMMU platform devices like IOAPIC are required to make > interrupt remapping requests using explicit SID.We affiliate an MSI > route with a requester ID and a PCI device if present which ensures > that platform devices can

Re: [Qemu-devel] [v4 2/6] hw/i386: enforce SID verification

On Mon, Sep 12, 2016 at 2:09 PM, Peter Xu wrote: > On Mon, Sep 12, 2016 at 01:08:05PM +0300, David Kiarie wrote: > > [...] > > > @@ -2252,14 +2250,17 @@ static MemTxResult vtd_mem_ir_write(void > *opaque, hwaddr addr, > > { > > int ret = 0; > > MSIMessage from = {},

Re: [Qemu-devel] [v4 2/6] hw/i386: enforce SID verification

On Mon, Sep 12, 2016 at 01:08:05PM +0300, David Kiarie wrote: > Platform devices are now able to make interrupt request with > explicit SIDs hence we can safely expect triggered AddressSpace ID > to match the requesting ID > > Signed-off-by: David Kiarie > --- >

[Qemu-devel] [PATCH 15/16] tcg: Make tb_flush() thread safe

From: Sergey Fedorov Use async_safe_run_on_cpu() to make tb_flush() thread safe. This is possible now that code generation does not happen in the middle of execution. It can happen that multiple threads schedule a safe work to flush the translation buffer. To keep

[Qemu-devel] [PATCH 05/16] linux-user: Add qemu_cpu_is_self() and qemu_cpu_kick()

From: Sergey Fedorov Signed-off-by: Sergey Fedorov Signed-off-by: Sergey Fedorov Reviewed-by: Alex Bennée Signed-off-by: Alex Bennée Message-Id:

[Qemu-devel] [PATCH 11/16] cpus-common: always defer async_run_on_cpu work items

async_run_on_cpu is only called from the I/O thread, not from CPU threads, so it doesn't make any difference. It will make a difference however for async_safe_run_on_cpu. Reviewed-by: Alex Bennée Signed-off-by: Paolo Bonzini --- cpus-common.c | 5

[Qemu-devel] [PULL v1 1/3] crypto: ensure XTS is only used with ciphers with 16 byte blocks

The XTS cipher mode needs to be used with a cipher which has a block size of 16 bytes. If a mis-matching block size is used, the code will either corrupt memory beyond the IV array, or not fully encrypt/decrypt the IV. This fixes a memory corruption crash when attempting to use cast5-128 with

Re: [Qemu-devel] [v4 2/6] hw/i386: enforce SID verification

On Mon, Sep 12, 2016 at 01:08:05PM +0300, David Kiarie wrote: [...] > @@ -2252,14 +2250,17 @@ static MemTxResult vtd_mem_ir_write(void *opaque, > hwaddr addr, > { > int ret = 0; > MSIMessage from = {}, to = {}; > -uint16_t sid = X86_IOMMU_SID_INVALID; > +VTDAddressSpace *as =

[Qemu-devel] [PATCH 14/16] cpus-common: Introduce async_safe_run_on_cpu()

Signed-off-by: Paolo Bonzini --- cpus-common.c | 25 +++-- include/qom/cpu.h | 11 +++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/cpus-common.c b/cpus-common.c index 12c8e69..50a92dd 100644 --- a/cpus-common.c +++

[Qemu-devel] [PATCH 06/16] cpus-common: move CPU list management to common code

Add a mutex for the CPU list to system emulation, as it will be used to manage safe work. Abstract manipulation of the CPU list in new functions cpu_list_add and cpu_list_remove. Signed-off-by: Paolo Bonzini --- Makefile.target | 2 +- bsd-user/main.c

[Qemu-devel] [PULL] Update OpenBIOS images

Hi Peter, This update to OpenBIOS brings in several PPC updates, but more importantly brings in the CPU context rework code which I'd like to get in at the start of the 2.8 cycle to shake out any issues as early as possible. Please pull. ATB, Mark. The following changes since commit

[Qemu-devel] [PATCH 12/16] cpus-common: remove redundant call to exclusive_idle()

No need to call exclusive_idle() from cpu_exec_end since it is done immediately afterwards in cpu_exec_start. Any exclusive section could run as soon as cpu_exec_end leaves, because cpu->running is false and the mutex is not taken, so the call does not add any protection either. Signed-off-by:

Re: [Qemu-devel] [PULL v2 00/14] virtio, vhost, pc: fixes and updates

On 9 September 2016 at 22:47, Michael S. Tsirkin wrote: > The following changes since commit c2a57aae9a1c3dd7de77daf5478df10379aeeebf: > > Merge remote-tracking branch 'remotes/famz/tags/docker-pull-request' into > staging (2016-09-09 12:49:41 +0100) > > are available in the

Re: [Qemu-devel] [PATCH] virtio-bus: Plug devices after features are negotiated

On Mon, 12 Sep 2016 11:18:52 +0200 Maxime Coquelin wrote: > On 09/12/2016 10:51 AM, Cornelia Huck wrote: > > On Sat, 10 Sep 2016 10:23:37 +0200 > > Maxime Coquelin wrote: > >> diff --git a/include/hw/virtio/virtio-bus.h > >>

[Qemu-devel] [PATCH 4/5] virtio-ccw: set revision 2 as maximal revision number

From: Pierre Morel We have everything needed for virtio-ccw revision 2 wired up now. Bump the maximum supported revision reported on a device basis to the guest so they can make use of it. Signed-off-by: Pierre Morel Signed-off-by: Cornelia

[Qemu-devel] [PATCH 0/5] s390x enhancements and fixes

Here are some s390x patches that have accumulated at my end: - fixup for the cpu model patches - support for READ_STATUS, which has been accepted into the upcoming virtio 1.1 standard - update MAINTAINERS file pattern Christian Borntraeger (2): s390x/kvm: disable cpu model for the 2.7 machine

[Qemu-devel] [PATCH 1/5] s390x/kvm: disable cpu model for the 2.7 machine

From: Christian Borntraeger cpu model was merged with 2.8, it is wrong to abuse ri_allowed which was enabled with 2.7. Signed-off-by: Christian Borntraeger Signed-off-by: Cornelia Huck --- hw/s390x/s390-virtio-ccw.c

[Qemu-devel] [PULL v1 3/3] crypto: report enum strings instead of values in errors

Several error messages print out the raw enum value, which is less than helpful to users, as these values are not documented, nor stable across QEMU releases. Switch to use the enum string instead. The nettle impl also had two typos where it mistakenly said "algorithm" instead of "mode", and

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