[Qemu-devel] [PULL 14/67] target-ppc: add vextu[bhw][lr]x instructions

From: Avinesh Kumar vextublx: Vector Extract Unsigned Byte Left vextuhlx: Vector Extract Unsigned Halfword Left vextuwlx: Vector Extract Unsigned Word Left vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form vextuhrx: Vector Extract Unsigned Halfword

[Qemu-devel] [PULL 08/67] target-ppc: implement stxsd and stxssp

From: Nikunj A Dadhania stxsd: Store VSX Scalar Dword stxssp: Store VSX Scalar SP Moreover, DQ-Form/DS-FORM instructions shares the same primary opcode(0x3D). For DQ-FORM bits 29:31 are used, for DS-FORM bits 30:31 are used. Common routine to decode primary

[Qemu-devel] [PULL 16/67] pseries: Make cpu_update during CAS unconditional

spapr_h_cas_compose_response() includes a cpu_update parameter which controls whether it includes updated information on the CPUs in the device tree fragment returned from the ibm,client-architecture-support (CAS) call. Providing the updated information is essential when CAS has negotiated

[Qemu-devel] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions

From: Nikunj A Dadhania lxsd: Load VSX Scalar Dword lxssp: Load VSX Scalar Single Moreover, DS-Form instructions shares the same primary opcode, bits 30:31 are used to decode the instruction. Use a common routine to decode primary opcode(0x39) - ds-form instructions

[Qemu-devel] [PULL 28/67] target-ppc: implement lxvll instruction

From: Nikunj A Dadhania lxvll: Load VSX Vector Left-justified with Length Little/Big-endian Storage: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|

[Qemu-devel] [PULL 29/67] target-ppc: implement stxvl instruction

From: Nikunj A Dadhania stxvl: Store VSX Vector with Length Vector (8-bit elements) in BE: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|

[Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic

During boot, PAPR guests negotiate CPU model support with the ibm,client-architecture-support mechanism. The logic to implement this in qemu is very convoluted. This cleans it up to be cleaner, using the new ppc_check_compat() call. The new logic for choosing a compatibility mode is: 1.

[Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <65e7ea6ea1cd0ebf291b1ed76d5cb1cccff2d49e.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 4 1 file changed, 4

[Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction

From: Nikunj A Dadhania xsxexpqp: VSX Scalar Extract Exponent Quad Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 15 +++

[Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <146ff5800a7da7599439d69c4bd907a0b51747aa.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- linux-user/main.c | 2 +-

Re: [Qemu-devel] [PATCH v2 2/2] memory: hmp: dump flat view for 'info mtree'

On Wed, Jan 11, 2017 at 06:13:11PM +0100, Paolo Bonzini wrote: > > > On 21/12/2016 08:58, Peter Xu wrote: > > Dumping flat view will be useful to debug the memory rendering logic, > > also it'll be much easier with it to know what memory region is handling > > what address range. > > > >

[Qemu-devel] [PATCH RFC v2 06/12] s390x/css: device support for s390-ccw passthrough

From: Xiao Feng Ren In order to support subchannels pass-through, we introduce a s390 subchannel device called "s390-ccw" to hold the real subchannel info. The s390-ccw devices inherit from the abstract CcwDevice which connect to the existing virtual-css-bus.

[Qemu-devel] [PATCH RFC v2 11/12] s390x/css: ccws translation infrastructure

From: Xiao Feng Ren Implement a basic infrastructure of handling channel I/O instruction interception for passed through subchannels: 1. Branch the code path of instruction interception handling by SubChannel type. 2. For a passed-through subchannel, issue the ORB

[Qemu-devel] [PATCH] doc/usb2: fix typo

Signed-off-by: Cao jin --- docs/usb2.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/usb2.txt b/docs/usb2.txt index c7a445afcd55..b9e75480737c 100644 --- a/docs/usb2.txt +++ b/docs/usb2.txt @@ -19,7 +19,7 @@ the controller so the USB 2.0 bus

[Qemu-devel] [PATCH RFC v2 08/12] vfio/ccw: get io region info

vfio-ccw provides an MMIO region for I/O operations. We fetch its information via ioctls here, then we can use it performing I/O instructions and retrieving I/O results later on. Signed-off-by: Xiao Feng Ren --- hw/vfio/ccw.c | 52

[Qemu-devel] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT

From: Nikunj A Dadhania Add _BIT to CRF_[GT,LT,EQ_SO] and introduce CRF_[GT,LT,EQ,SO] for usage without shifts in the code. This would simplify the code. Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson

[Qemu-devel] [PULL 02/67] target-ppc: Consolidate instruction decode helpers

From: Bharata B Rao Move instruction decode helpers to target-ppc/internal.h so that some of these can be used from outside of translate.c. This movement also helps to get rid of some duplicate helpers from target-ppc/fpu_helper.c. Suggested-by: Nikunj A Dadhania

[Qemu-devel] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction

From: Jose Ricardo Ziviani bcdsetsgn.: Decimal set sign. This instruction copies the register value to the result register but adjust the signal according to the preferred sign value. Signed-off-by: Jose Ricardo Ziviani Reviewed-by: David

[Qemu-devel] [PULL 25/67] target-ppc: implement xscpsgnqp instruction

From: Nikunj A Dadhania xscpsgnqp: VSX Scalar Copy Sign Quad-Precision Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions

From: Bharata B Rao xscmpexpdp: VSX Scalar Compare Exponents Double-Precision xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by:

[Qemu-devel] [PULL 24/67] target-ppc: implement xsnegqp instruction

From: Nikunj A Dadhania xsnegqp: VSX Scalar Negate Quad-Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 4

[Qemu-devel] [PULL 38/67] qtest: add display-vga-test to ppc64

From: Laurent Vivier Only enable for ppc64 in the Makefile, but added code in the file to check cirrus card only on architectures supporting it (alpha, mips, i386, x86_64). Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth

[Qemu-devel] [PULL 41/67] qtest: add ivshmem-test for ppc64

From: Laurent Vivier The test has been converted to use libqos, we can now use it on ppc64. We also make the test fail on all other architectures. As libqos on ppc64 is not able to manage hotplug and IRQ/MSI, we disable this part in the test on ppc64. Signed-off-by: Laurent

[Qemu-devel] [PULL 67/67] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro

From: Jose Ricardo Ziviani This commit fixes a warning in the code "(i * 2) ? .. : ..", which should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE macro by placing parentheses around its argument to avoid possible expansion issues like: BCD_DIG_BYTE(i + j).

[Qemu-devel] [PULL 55/67] target-ppc: Use correct precision for FPRF setting

From: Bharata B Rao Use correct FP precision when setting FPRF in FP conversion helpers instead of always assuming float64 precision. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by:

[Qemu-devel] [PULL 56/67] target-ppc: Add xsxexpdp instruction

From: Nikunj A Dadhania xsxexpdp: VSX Scalar Extract Exponent Dual Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 13 +

[Qemu-devel] [PULL 42/67] hw/gpio: QOM'ify mpc8xxx.c

From: xiaoqiang zhao * Drop the old SysBus init function and use instance_init * Change mpc8xxx_gpio_reset to a DeviceClass::reset function Signed-off-by: xiaoqiang zhao Signed-off-by: David Gibson --- hw/gpio/mpc8xxx.c |

[Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction

From: Nikunj A Dadhania xxinsertw: VSX Vector Insert Word Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/int_helper.c | 25

[Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers

From: Artyom Tarasenko Use explicit register pointers while accessing D/I-MMU registers. Call cpu_unassigned_access on access to missing registers. Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id:

[Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format

From: Artyom Tarasenko According to chapter 13.3 of the UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005, only the sun4u format is available for data-access loads. Store UA2005 entries in the sun4u format to simplify processing. Signed-off-by: Artyom Tarasenko

Re: [Qemu-devel] [PATCH qemu 2/2] spapr_pci: Advertise 16M IOMMU pages when available

On Mon, Jan 09, 2017 at 01:06:03PM +1100, Alexey Kardashevskiy wrote: > On 03/01/17 10:41, David Gibson wrote: > > On Thu, Dec 22, 2016 at 04:22:12PM +1100, Alexey Kardashevskiy wrote: > >> On sPAPR, IOMMU page size varies and if QEMU is running with RAM > >> backed with hugepages, we can

Re: [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction

On Thu, Jan 12, 2017 at 10:23:22AM +0530, Nikunj A Dadhania wrote: > David Gibson writes: > > > [ Unknown signature status ] > > On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote: > >> xsiexpdp: VSX Scalar Insert Exponent Double Precision > >> > >>

[Qemu-devel] [PATCH RFC v2 00/15] basic vfio-ccw infrastructure

vfio-ccw: the basic infrastructure == Introduction Here we describe the vfio support for I/O subchannel devices for Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a virtual machine, while vfio is the means. Different than other

[Qemu-devel] [PATCH RFC v2 03/15] vfio: ccw: define device_api strings

Define vfio-ccw device API strings. CCW vendor driver using mediated device framework should use this string for device_api attribute. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel --- include/uapi/linux/vfio.h | 1 + 1 file

[Qemu-devel] [PATCH RFC v2 04/15] vfio: ccw: basic implementation for vfio_ccw driver

To make vfio support subchannel devices, we need a css driver for the vfio subchannels. This patch adds a basic vfio-ccw subchannel driver for this purpose. To enable VFIO for vfio-ccw, enable S390_CCW_IOMMU config option and configure VFIO as required. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 01/15] s390: cio: introduce cio_cancel_halt_clear

For future code reuse purpose, this decouples the cio code with the ccw device specific parts from ccw_device_cancel_halt_clear, and makes a new common I/O interface named cio_cancel_halt_clear. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel

[Qemu-devel] [PULL 12/67] target-ppc: Implement bcdcpsgn. instruction

From: Jose Ricardo Ziviani bcdcpsgn.: Decimal copy sign. Given two registers vra and vrb, it copies the vra value with vrb sign to the result register vrt. Signed-off-by: Jose Ricardo Ziviani Reviewed-by: David Gibson

[Qemu-devel] [PULL 21/67] target-ppc: implement stop instruction

From: Nikunj A Dadhania Use the nap code. Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

[Qemu-devel] [PULL 00/30] target-sparc sun4v support

-sparc-20170111 for you to fetch changes up to 224be7cc93a37ccd38342811a8925de889de1a49: target-sparc: fix up niagara machine (2017-01-11 12:23:58 -0800) Sun4v support

[Qemu-devel] [PULL 34/67] ppc: Rewrite ppc_set_compat()

This rewrites the ppc_set_compat() function so that instead of open coding the various compatibility modes, it reads the relevant data from a table. This is a first step in consolidating the information on compatibility modes scattered across the code into a single place. It also makes one change

[Qemu-devel] [PULL 66/67] ppc: Prevent inifnite loop in decrementer auto-reload.

From: Roman Kapl If the DECAR register is set to 0, QEMU tries to reload the decrementer with zero in an inifinite loop. According to PPC documentation, the decrementer is triggered on 1->0 transition, so avoid reloading the decrementer if if is already zero. The problem does

[Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode

From: Artyom Tarasenko Please note that QEMU doesn't impelement Real->Physical address translation. The "Real Address" is always the "Physical Address". Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko Message-Id:

[Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <2bf424bff7e4dee34fcbcada4fd490205f392823.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 22

[Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <6139718b8d11c9c893d6deb02431c615ef422d65.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/translate.c | 2 +- 1 file changed, 1

[Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <70562e4ef094e2beb2c56380fdd0db7b15cc0294.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH] linux-user: Use *at functions instead of caching interp_prefix contents

If the interp_prefix is a complete chroot, it may have a *lot* of files. Setting up the cache for this is quite expensive. Instead, use the *at versions of various syscalls to attempt the operation in the prefix. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 12

Re: [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests

On Tue, Jan 10, 2017 at 08:34:29AM -0600, Eric Blake wrote: > On 01/09/2017 08:10 PM, Jose Ricardo Ziviani wrote: > > Implements 128-bit left shift and right shift as well as their > > testcases. By design, shift silently mods by 128, so the caller is > > responsible to assert the shift range if

[Qemu-devel] [kvm-unit-tests PATCH v6 2/3] run_tests: put logs into per-test file

We were using test.log before to keep all the test logs. This patch creates one log file per test case under logs/ directory with name "TESTNAME.log". Meanwhile, we will keep the last time log into logs.old/. Renaming scripts/functions.bash into scripts/common.bash to store some more global

[Qemu-devel] Question about io mode & cache mode

Hello. I sent mail for question about io mode and cache mode. When I set VM to I/O mode = native and cache mode = none, Vm cannot boot and vm is turn off automatically. Why cannot VM boot?

[Qemu-devel] [PATCH RFC v2 09/12] vfio/ccw: get irqs info and set the eventfd fd

From: Xiao Feng Ren vfio-ccw resorts to the eventfd mechanism to communicate with userspace. We fetch the irqs info via the ioctl VFIO_DEVICE_GET_IRQ_INFO, register a event notifier to get the eventfd fd which is sent to kernel via the ioctl VFIO_DEVICE_SET_IRQS,

[Qemu-devel] [PATCH RFC v2 12/12] vfio/ccw: update sense data if a unit check is pending

Concurrent-sense data is currently not delivered. This patch stores the concurrent-sense data to the subchannel if a unit check is pending and the concurrent-sense bit is enabled. Then a TSCH can retreive the right IRB data back to the guest. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PULL 35/67] ppc: Rewrite ppc_get_compat_smt_threads()

To continue consolidation of compatibility mode information, this rewrites the ppc_get_compat_smt_threads() function using the table of compatiblity modes in target-ppc/compat.c. It's not a direct replacement, the new ppc_compat_max_threads() function has simpler semantics - it just returns the

[Qemu-devel] [PULL 45/67] hw/ppc: QOM'ify spapr_vio.c

From: xiaoqiang zhao Drop the old and empty SysBus init Signed-off-by: xiaoqiang zhao Signed-off-by: David Gibson --- hw/ppc/spapr_vio.c | 10 -- 1 file changed, 10 deletions(-) diff --git a/hw/ppc/spapr_vio.c

[Qemu-devel] [PULL 40/67] qtest: convert ivshmem-test to use libqos

From: Laurent Vivier This will allow to use it with ppc64. Signed-off-by: Laurent Vivier Signed-off-by: David Gibson --- tests/ivshmem-test.c | 31 +-- 1 file changed, 17 insertions(+), 14

[Qemu-devel] [PULL 50/67] prep: add IBM RS/6000 7020 (40p) machine emulation

From: Hervé Poussineau Machine supports both Open Hack'Ware and OpenBIOS. Open Hack'Ware is the default because OpenBIOS is currently unable to boot PReP boot partitions or PReP kernels. Signed-off-by: Hervé Poussineau [dwg: Correct compile failure

[Qemu-devel] [PULL 26/67] target-ppc: Add xxperm and xxpermr instructions

From: Bharata B Rao xxperm: VSX Vector Permute xxpermr: VSX Vector Permute Right-indexed Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson

[Qemu-devel] [PULL 63/67] target-ppc: Add xsaddqp instructions

From: Bharata B Rao xsaddqp: VSX Scalar Add Quad-Precision Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/fpu_helper.c

[Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64

From: Laurent Vivier Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth Reviewed-by: Greg Kurz Tested-by: Greg Kurz Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB

From: Artyom Tarasenko Suggested-by: Richard Henderson Signed-off-by: Artyom Tarasenko Message-Id: Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <83b315e3527bef56741c84e6d4f98de9bea2c560.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 +

[Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <288f09c6282bf46af7ad8343fe63f7438a9f44a2.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 1/2] run_tests: put logs into per-test file

On Wed, Jan 11, 2017 at 11:46:38AM +0100, Andrew Jones wrote: [...] > > So, how about this: > > > > rm -rf $unittest_log_dir.old || err "Failed remove old logs" > > if [[ -d $unittest_log_dir ]]; then > > Only [ ... ] for tests like these I thought [[ ... ]] would be superior to [ ...

[Qemu-devel] [PATCH RFC v2 00/12] basic channel IO passthrough infrastructure based on vfio

The patch series introduce a basic channel I/O passthrough infrastructure based on vfio. - Focus on supporting dasd-eckd(cu_type/dev_type = 0x3990/0x3390) as the target device. - Support new qemu parameters in the style of: "-machine s390-ccw-virtio(,s390-map-css=on|off) ... -device

[Qemu-devel] [PATCH RFC v2 05/12] s390x/css: realize css_create_sch

The S390 virtual css support already has a mechanism to create a virtual subchannel and provide it to the guest. However, to pass-through subchannels to a guest, we need to introduce a new mechanism to create the subchannel according to the real device information. Thus we realize a new

[Qemu-devel] [PATCH RFC v2 10/12] s390x/css: introduce and realize ccw-request callback

From: Xiao Feng Ren Introduce a new callback on subchannel to handle ccw-request. Realize the callback in vfio-ccw device. Besides, resort to the event notifier handler to handling the ccw-request results. 1. Pread the I/O results via MMIO region. 2. Update the scsw

[Qemu-devel] [PATCH RFC v2 03/12] s390x/css: add s390-map-css machine option

From: Xiao Feng Ren We want to support real (i.e. not virtual) channel devices even for guests that do not support MCSS-E (where guests may see devices from any channel subsystem image at once). As all virtio-ccw devices are in css 0xfe (and show up in the default

[Qemu-devel] [PULL 30/67] target-ppc: implement stxvll instructions

From: Nikunj A Dadhania stxvll: Store VSX Vector Left-justified with Length Vector (8-bit elements) in BE/LE: +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|

[Qemu-devel] [PULL 49/67] prep: add IBM RS/6000 7020 (40p) memory controller

From: Hervé Poussineau Signed-off-by: Hervé Poussineau Reviewed-by: David Gibson [dwg: Added CONFIG_RS6000_MC to ppc64 or it breaks testcases] Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 44/67] hw/ppc: QOM'ify ppce500_spin.c

From: xiaoqiang zhao Drop the old SysBus init function and use instance_init Signed-off-by: xiaoqiang zhao Signed-off-by: David Gibson --- hw/ppc/ppce500_spin.c | 18 -- 1 file changed, 8 insertions(+), 10

[Qemu-devel] [PULL 60/67] pxb: Restrict to x86

The PCI Expander Bridge (PXB) device is essentially a hack to allow different PCIe devices to be assigned to different NUMA nodes on x86. Each PXB is sort-of a separate PCI host bridge, except that its config space is shared with the config space of the main PCI host bridge, rather than being

[Qemu-devel] [PULL 52/67] target-ppc: Replace isden by float64_is_zero_or_denormal

From: Bharata B Rao Replace isden() by float64_is_zero_or_denormal() so that code in helper_compute_fprf() can be reused to work with float128 argument. Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode

From: Artyom Tarasenko while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko Message-Id:

Re: [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11

On Tue, Jan 10, 2017 at 02:20:32PM +0530, Nikunj A Dadhania wrote: > This series contains 10 new instructions for POWER9 ISA3.0 > VSX Scalar Insert Exponent > VSX Vector Insert Exponent > VSX Vector Extract Exponent/Significand > VSX Scalar Truncate & Convert Quad-Precision >

[Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <660569980c8449b732c19338412af241f216a563.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [kvm-unit-tests PATCH v6 0/3] run_tests: support concurrent test execution

v6: - some tunes on how to rm/mv logs/logs.old [Drew] - fix errno to 2 when param parse fail [Drew] - add one more patch to fix *) case errno [Drew] (please either take/squash/... this one) - comment fix again [Drew] v5: - add "/" at start/end of line where proper [Drew] - remove useless

Re: [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part

On Tue, Jan 10, 2017 at 12:10:07AM -0200, Jose Ricardo Ziviani wrote: > v5: > - removes 'unlikely' gcc branch pred. hints from not unlikely places > - adds comments in host-utils functions > - adds more test cases for shift functions > - handles "shift backwards" with signed shifts > -

Re: [Qemu-devel] [PATCH] Further tidy-up on block status

11.01.2017 22:00, Alex Bligh wrote: On 11 Jan 2017, at 15:31, Vladimir Sementsov-Ogievskiy wrote: If an error occurs, the server SHOULD set the appropriate error code in the error field of an error chunk. However, if the error does not involve invalid usage (such

[Qemu-devel] [PATCH V1 1/4] target-arm: Add support for PMU register PMSELR_EL0

This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang --- target/arm/cpu.h| 1 + target/arm/helper.c | 24 +++- 2 files changed, 20 insertions(+), 5 deletions(-) diff

[Qemu-devel] [PATCH V1 0/4] Add vPMU vPMU support under TCG mode

QEMU has implemented cycle count support for guest VM under TCG mode. But this feature is not complete. In fact using perf inside a 64-bit Linux guest VM (under TCG) can cause the following kernel panic because some PMU registers are not implemented. [ 329.445970] []

[Qemu-devel] [PATCH RFC v2 10/15] vfio: ccw: realize VFIO_DEVICE_RESET ioctl

Introduce VFIO_DEVICE_RESET ioctl for vfio-ccw to make it possible to hot-reset the device. We try to achieve a reset by first disabling the subchannel and then enabling it again: this should clear all state at the subchannel. Signed-off-by: Dong Jia Shi ---

[Qemu-devel] [PATCH RFC v2 06/15] vfio: ccw: register vfio_ccw to the mediated device framework

To make vfio support subchannel devices, we need to leverage the mediated device framework to create a mediated device for the subchannel device. This registers the subchannel device to the mediated device framework during probe to enable mediated device creation. Signed-off-by: Dong Jia Shi

[Qemu-devel] [PATCH RFC v2 02/15] s390: cio: export more interfaces

Export the common I/O interfaces those are needed by an I/O subchannel driver to actually talk to the subchannel. Signed-off-by: Dong Jia Shi Reviewed-by: Pierre Morel --- drivers/s390/cio/cio.c | 10 ++ 1 file changed, 10

[Qemu-devel] [PATCH RFC v2 07/12] vfio/ccw: vfio based subchannel passthrough driver

From: Xiao Feng Ren We use the IOMMU_TYPE1 of VFIO to realize the subchannels passthrough, implement a vfio based subchannels passthrough driver called "vfio-ccw". Support qemu parameters in the style of: "-device vfio-ccw,id=xx,hostid=xx(,guestid=xx),mdevid=xx"

[Qemu-devel] [PATCH RFC v2 15/15] vfio: ccw: introduce support for ccw0

Although Linux does not use format-0 channel command words (CCW0) these are a non-optional part of the platform spec, and for the sake of platform compliance, and possibly some non-Linux guests, we have to support CCW0. Making the kernel execute a format 0 channel program is too much hassle

[Qemu-devel] [PULL 33/67] pseries: Add pseries-2.9 machine type

Signed-off-by: David Gibson Reviewed-by: Thomas Huth Reviewed-by: Laurent Vivier --- hw/ppc/spapr.c | 23 +-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c

[Qemu-devel] [PULL 36/67] ppc: Validate compatibility modes when setting

Current ppc_set_compat() will attempt to set any compatiblity mode specified, regardless of whether it's available on the CPU. The caller is expected to make sure it is setting a possible mode, which is awkwward because most of the information to make that decision is at the CPU level. This

[Qemu-devel] [PULL 19/67] ppc/spapr: implement H_SIGNAL_SYS_RESET

From: Nicholas Piggin The H_SIGNAL_SYS_RESET hcall allows a guest CPU to raise a system reset exception on CPUs within the same guest -- all CPUs, all-but-self, or a specific CPU (including self). This has not made its way to a PAPR release yet, but we have an hcall number

[Qemu-devel] [PULL 31/67] hw/ppc/spapr: Fix boot path of usb-host storage devices

From: Thomas Huth When passing through an USB storage device to a pseries guest, it is currently not possible to automatically boot from the device if the "bootindex" property has been specified, too (e.g. when using "-device nec-usb-xhci -device

[Qemu-devel] [PULL 62/67] ppc: Add ppc_set_compat_all()

Once a compatiblity mode is negotiated with the guest, h_client_architecture_support() uses run_on_cpu() to update each CPU to the new mode. We're going to want this logic somewhere else shortly, so make a helper function to do this global update. We put it in target-ppc/compat.c - it makes as

[Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction

From: Nikunj A Dadhania xxextractuw: VSX Vector Extract Unsigned Word Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/int_helper.c

[Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson Message-Id: <0fcf7eca7c2d3e6bef7846027857da3bd681645d.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson ---

[Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction

From: Bharata B Rao xscvdpqp: VSX Scalar Convert Double-Precision format to Quad-Precision format Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson

[Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode

From: Artyom Tarasenko As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005, outstanding disrupting exceptions that are destined for privileged mode can only cause a trap when the virtual processor is in nonprivileged or privileged mode and PSTATE.ie = 1. At

Re: [Qemu-devel] [PATCH] nvdimm acpi: fix g_array_free() with NULL pointer

On 01/11/2017 05:36 PM, Stefan Hajnoczi wrote: Unlike g_free(), g_array_free() does not accept a NULL pointer argument. The following error is logged when an nvdimm device is realized: GLib-CRITICAL **: g_array_free: assertion 'array' failed Cc: Xiao Guangrong

[Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <7edada4d1c26562843de80c9eb2339ca591f883b.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 1 +

[Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left

From: Artyom Tarasenko Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced."

Re: [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction

On Tue, Jan 10, 2017 at 12:10:13AM -0200, Jose Ricardo Ziviani wrote: > bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the > number of bytes to truncate in vra, the return register will have vrb > with such bits truncated. > > Signed-off-by: Jose Ricardo Ziviani

[Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21)

From: Artyom Tarasenko Signed-off-by: Artyom Tarasenko Message-Id: <6f546cf963e03ed253e16701ba6e30dcc5d00073.1484165352.git.atar4q...@gmail.com> Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 31

Re: [Qemu-devel] [kvm-unit-tests PATCH v5 2/2] run_tests: allow run tests in parallel

On Wed, Jan 11, 2017 at 02:09:34PM +0100, Andrew Jones wrote: > On Wed, Jan 11, 2017 at 12:00:23PM +0100, Andrew Jones wrote: > > On Wed, Jan 11, 2017 at 01:29:35PM +0800, Peter Xu wrote: > > > run_task.sh is getting slow. This patch is trying to make it faster by > > > running the tests

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