Re: [Qemu-devel] [PATCH 1/2] hw/hppa: Use qemu_log_mask instead of fprintf to stderr

2018-02-04 Thread Alex Bennée
Richard Henderson writes: > Reported-by: Thomas Huth > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée > --- > hw/hppa/machine.c | 17 - > 1 file changed, 8

Re: [Qemu-devel] [PATCH 00/24] re-factor and add fp16 using glibc soft-fp

2018-02-04 Thread Peter Maydell
On 4 February 2018 at 04:11, Richard Henderson wrote: > Or there's the code from glibc. I know Peter didn't like the idea; > debugging this code is fairly painful -- the massive preprocessor > macros mean that you can't step through anything. But at least we > have

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
On Tue, Jan 9, 2018 at 3:31 AM, Christoph Hellwig wrote: > On Wed, Jan 03, 2018 at 01:44:15PM +1300, Michael Clark wrote: > > HTIF (Host Target Interface) provides console emulation for QEMU. HTIF > > allows identical copies of BBL (Berkeley Boot Loader) and linux to run > > on both

Re: [Qemu-devel] [PATCH] rtc: placing RTC memory region outside BQL

2018-02-04 Thread Peter Maydell
On 1 February 2018 at 14:23, Paolo Bonzini wrote: > On 01/02/2018 08:47, Gonglei wrote: >> diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c >> index 35a05a6..d9d99c5 100644 >> --- a/hw/timer/mc146818rtc.c >> +++ b/hw/timer/mc146818rtc.c >> @@ -986,6 +986,7 @@

Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure

2018-02-04 Thread Michael Clark
On Fri, Jan 12, 2018 at 7:43 AM, Michael Clark wrote: > > > On Fri, Jan 12, 2018 at 3:05 AM, Eric Blake wrote: > >> On 01/10/2018 08:22 PM, Michael Clark wrote: >> > This adds RISC-V into the build system enabling the following targets: >> > >> > -

Re: [Qemu-devel] [virtio-dev] Re: [PATCH v1 6/6] vhost-user: add VFIO based accelerators support

2018-02-04 Thread Alexander Duyck
On Thu, Jan 25, 2018 at 9:57 PM, Tiwei Bie wrote: > On Fri, Jan 26, 2018 at 11:41:27AM +0800, Jason Wang wrote: >> On 2018年01月26日 07:59, Michael S. Tsirkin wrote: >> > > The virtual IOMMU isn't supported by the accelerators for now. >> > > Because vhost-user currently lacks

[Qemu-devel] [PULL 1/3] hw/hppa: Use qemu_log_mask instead of fprintf to stderr

2018-02-04 Thread Richard Henderson
Reviewed-by: Alex Bennée Reported-by: Thomas Huth Signed-off-by: Richard Henderson --- hw/hppa/machine.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/hppa/machine.c

[Qemu-devel] [PULL 0/3] hppa-softmmu update

2018-02-04 Thread Richard Henderson
://github.com/rth7680/qemu.git tags/pull-hppa-20180204 for you to fetch changes up to edf90bd0af98bf03ec1e60e5c7632774f62837d8: roms/seabios-hppa: Update submodule and image (2018-02-04 14:11:18 -0800) hppa-softmmu update

[Qemu-devel] [PATCH] hw/char/stm32f2xx_usart: improve TXE/TC bit handling

2018-02-04 Thread Richard Braun
Consider that data is always immediately sent. As a result, keep the SR_TXE and SR_TC bits always set. In addition, fix the reset value of the USART status register. Signed-off-by: Richard Braun --- hw/char/stm32f2xx_usart.c | 4 include/hw/char/stm32f2xx_usart.h

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

2018-02-04 Thread Christoph Hellwig
On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote: > BTW I've created branches in my own personal trees for Privileged ISA > v1.9.1. These trees are what I use for v1.9.1 backward compatibility > testing in QEMU: > > -

[Qemu-devel] [PULL 2/3] tests: Enable boot-serial-test for hppa

2018-02-04 Thread Richard Henderson
Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson --- tests/boot-serial-test.c | 1 + tests/Makefile.include | 2 ++ 2 files changed, 3 insertions(+) diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c index

Re: [Qemu-devel] [PATCH v1 11/21] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
On Mon, Feb 5, 2018 at 10:29 AM, Christoph Hellwig wrote: > On Mon, Feb 05, 2018 at 09:19:46AM +1300, Michael Clark wrote: > > BTW I've created branches in my own personal trees for Privileged ISA > > v1.9.1. These trees are what I use for v1.9.1 backward compatibility > > testing

[Qemu-devel] [PATCH v4 00/22] RISC-V QEMU Port Submission

2018-02-04 Thread Michael Clark
QEMU RISC-V Emulation Support (RV64GC, RV32GC) This patch series contains a number of bug fixes and code cleanups incorporates changes from Richard Henderson's tree: - https://github.com/rth7680/qemu/tree/tgt-riscv The git tree for this v4 patch series (squashed and rebased): -

Re: [Qemu-devel] [RFC PATCH qemu] qmp: Add qom-list-properties to list QOM object properties

2018-02-04 Thread Alexey Kardashevskiy
On 02/02/18 18:37, Markus Armbruster wrote: > Alexey Kardashevskiy writes: > >> On 01/02/18 04:22, Markus Armbruster wrote: >>> Alexey Kardashevskiy writes: >>> There is already 'device-list-properties' which does most of the job, however it does not

Re: [Qemu-devel] [PATCH v7 10/15] hw/sd: Replace fprintf(stderr, "*\n" with error_report()

2018-02-04 Thread Markus Armbruster
Thomas Huth writes: > On 02.02.2018 19:37, Markus Armbruster wrote: >> From: Alistair Francis >> >> Replace a large number of the fprintf(stderr, "*\n" calls with >> error_report(). The functions were renamed with these commands and then >>

Re: [Qemu-devel] [PATCH v8 14/14] target: Use qemu_log() instead of fprintf(stderr, ...)

2018-02-04 Thread Thomas Huth
On 05.02.2018 07:33, Markus Armbruster wrote: > Thomas Huth writes: > >> On 03.02.2018 09:43, Markus Armbruster wrote: >>> From: Alistair Francis >>> >>> Convert fprintf(stderr, ...) to use qemu_log(). Double prints in >>> target/ppc/translate.c

Re: [Qemu-devel] [PATCH v4 10/51] qapi: add #if/#endif helpers

2018-02-04 Thread Markus Armbruster
Marc-André Lureau writes: > Add helpers to wrap generated code with #if/#endif lines. > > Add a function decorator that will be used to wrap visitor methods. > The decorator will check if code was generated before adding #if/#endif > lines. Used in the following

[Qemu-devel] [PATCH v2 0/3] s390x/pci: fixup and optimize IOTLB code

2018-02-04 Thread Yi Min Zhao
This series contains three patches, 1) optimizes the code including walking DMA tables and rpcit handler 2) fixes the issue caused by IOTLB global refresh 3) uses the right pal and pba when registering ioat The issue mentioned above was found when we tested SMC-r tools. This behavior has been

[Qemu-devel] [PATCH v2 2/3] s390x/pci: fixup global refresh

2018-02-04 Thread Yi Min Zhao
The VFIO common code doesn't provide the possibility to modify a previous mapping entry in another way than unmapping and mapping again with new properties. To avoid -EEXIST DMA mapping error, we introduce a GHashTable to store S390IOTLBEntry instances in order to cache the mapped entries. When

[Qemu-devel] [PATCH v2 1/3] s390x/pci: fixup the code walking IOMMU tables

2018-02-04 Thread Yi Min Zhao
Current s390x PCI IOMMU code is lack of flags' checking, including: 1) protection bit 2) table length 3) table offset 4) intermediate tables' invalid bit 5) format control bit This patch introduces a new struct named S390IOTLBEntry, and makes up these missed checkings. At the same time, inform

[Qemu-devel] [PATCH v2 3/3] s390x/pci: use the right pal and pba in reg_ioat()

2018-02-04 Thread Yi Min Zhao
When registering ioat, pba should be comprised of leftmost 52 bits and rightmost 12 binary zeros, and pal should be comprised of leftmost 52 bits and right most 12 binary ones. The lower 12 bits of words 5 and 7 of the FIB are ignored by the facility. Let's fixup this. Reviewed-by: Pierre Morel

[Qemu-devel] [Bug 1736655] Re: 2k3/xp guests w/virtio-net randomly DHCP fail on boot

2018-02-04 Thread Launchpad Bug Tracker
[Expired for qemu (Ubuntu) because there has been no activity for 60 days.] ** Changed in: qemu (Ubuntu) Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1736655

[Qemu-devel] [Bug 1736655] Re: 2k3/xp guests w/virtio-net randomly DHCP fail on boot

2018-02-04 Thread Launchpad Bug Tracker
[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1736655 Title: 2k3/xp

Re: [Qemu-devel] [PATCH v2 1/2] Add a git-publish configuration file

2018-02-04 Thread Michael Roth
Quoting Fam Zheng (2018-02-02 00:34:11) > git-publish [1] is a convenient tool to send patches and has been > popular among QEMU developers. Recently it has been made available in > Fedora official repo thanks to Stefan's work. > > One nice feature of the tool is a per-project configuration with

Re: [Qemu-devel] [PATCH v2 2/2] README: Document 'git-publish' workflow

2018-02-04 Thread Michael Roth
Quoting Fam Zheng (2018-02-02 00:34:12) > Signed-off-by: Fam Zheng > --- > .gitpublish | 1 + > README | 30 +- > 2 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/.gitpublish b/.gitpublish > index 170bd2ed48..7542e878fc 100644

[Qemu-devel] [PATCH v3 2/2] README: Document 'git-publish' workflow

2018-02-04 Thread Fam Zheng
Signed-off-by: Fam Zheng --- README | 30 +- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/README b/README index b92a07a61a..d1a944ce20 100644 --- a/README +++ b/README @@ -56,7 +56,7 @@ The QEMU source code is maintained under the GIT

Re: [Qemu-devel] [PATCH v4 01/51] qlit: use QType instead of int

2018-02-04 Thread Markus Armbruster
Marc-André Lureau writes: > Suggested-by: Markus Armbruster > Signed-off-by: Marc-André Lureau > --- > include/qapi/qmp/qlit.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [Qemu-devel] [PATCH v4 07/51] qapi: leave the ifcond attribute undefined until check()

2018-02-04 Thread Markus Armbruster
Marc-André Lureau writes: > We commonly initialize attributes to None in .init(), then set their > real value in .check(). Accessing the attribute before .check() > yields None. If we're lucky, the code that accesses the attribute > prematurely chokes on None. > >

[Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

2018-02-04 Thread Michael Clark
Add CPU state header, CPU definitions and initialization routines Signed-off-by: Michael Clark --- target/riscv/cpu.c | 385 target/riscv/cpu.h | 256 + target/riscv/cpu_bits.h | 417

[Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers

2018-02-04 Thread Michael Clark
Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark --- target/riscv/helper.c| 464 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c | 644

[Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation

2018-02-04 Thread Michael Clark
TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II:

[Qemu-devel] [PATCH v4 16/22] RISC-V VirtIO Machine

2018-02-04 Thread Michael Clark
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark --- hw/riscv/virt.c | 375

[Qemu-devel] [PATCH v4 21/22] SiFive Freedom U500 RISC-V Machine

2018-02-04 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark --- hw/riscv/sifive_u500.c | 338 +

[Qemu-devel] [PATCH v4 14/22] SiFive RISC-V PLIC Block

2018-02-04 Thread Michael Clark
The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_plic.c | 554 +

[Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection

2018-02-04 Thread Michael Clark
Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be

[Qemu-devel] [PATCH v4 11/22] RISC-V HTIF Console

2018-02-04 Thread Michael Clark
HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIF interface

Re: [Qemu-devel] [PATCH v8 14/14] target: Use qemu_log() instead of fprintf(stderr, ...)

2018-02-04 Thread Markus Armbruster
Thomas Huth writes: > On 03.02.2018 09:43, Markus Armbruster wrote: >> From: Alistair Francis >> >> Convert fprintf(stderr, ...) to use qemu_log(). Double prints in >> target/ppc/translate.c were manually remove. A fprintf() in >>

Re: [Qemu-devel] [PATCH] vfio/pci: Add option to disable GeForce quirks

2018-02-04 Thread Alex Williamson
On Mon, 29 Jan 2018 13:23:50 -0700 Alex Williamson wrote: > These quirks are necessary for GeForce, but not for Quadro/GRID/Tesla > assignment. Leaving them enabled is fully functional and provides the > most compatibility, but due to the unique NVIDIA MSI ACK

[Qemu-devel] [PATCH v4 19/22] SiFive RISC-V Test Finisher

2018-02-04 Thread Michael Clark
Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark --- hw/riscv/sifive_test.c | 99 ++ include/hw/riscv/sifive_test.h | 48 2 files changed, 147 insertions(+) create mode

[Qemu-devel] [PATCH v3 1/2] Add a git-publish configuration file

2018-02-04 Thread Fam Zheng
git-publish [1] is a convenient tool to send patches and has been popular among QEMU developers. Recently it has been made available in Fedora official repo thanks to Stefan's work. One nice feature of the tool is a per-project configuration with profiles, especially in which the cccmd option is

[Qemu-devel] [PATCH v3 0/2] Add git-publish config file

2018-02-04 Thread Fam Zheng
v3: Fix trivial hunk placement. [Michael] Fix PPC sub-list. [Michael] v2: Add README paragraph [Marc-André, Stefan] Fix 'trivial' profile [Marc-André] Rename profiles [Stefan] Fam Zheng (2): Add a git-publish configuration file README: Document 'git-publish' workflow

Re: [Qemu-devel] [PATCH v4 05/51] qapi: add 'if' to top-level expressions

2018-02-04 Thread Markus Armbruster
Marc-André Lureau writes: > Accept 'if' key in top-level elements, accepted as string or list of > string type. The following patches will modify the test visitor to > check the value is correctly saved, and generate #if/#endif code (as a > single #if/endif line or a

Re: [Qemu-devel] [PATCH] kvm: check dev parameter when updating msi route

2018-02-04 Thread P J P
Hello Radim, +-- On Fri, 2 Feb 2018, Radim Krčmář wrote --+ | This should primarily go to the qemu devel list. I've Cc'd it, but | reposting would be safer, thanks. Ah, Okay. I did think qemu-devel would be better, but MAINTAINERS file lists k...@vger.kernel.org address for accel/kvm/.

Re: [Qemu-devel] [PATCH v4 06/51] qapi: pass 'if' condition into QAPISchemaEntity objects

2018-02-04 Thread Markus Armbruster
Marc-André Lureau writes: > Built-in objects remain unconditional. Explicitly defined objects > use the condition specified in the schema. Implicitly defined > objects inherit their condition from their users. For most of them, > there is exactly one user, so the

[Qemu-devel] [PATCH] kvm: check dev parameter when updating msi route

2018-02-04 Thread P J P
From: Prasad J Pandit When updating message signalled interrupt(MSI) route in routine kvm_irqchip_update_msi_route, device parameter could be null. Add check to avoid null dereference. Reported-by: Guoxiang Niu Signed-off-by: Prasad J Pandit

[Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub

2018-02-04 Thread Michael Clark
GDB Register read and write routines. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- target/riscv/gdbstub.c | 60 ++ 1 file changed, 60 insertions(+) create mode 100644

[Qemu-devel] [PATCH v4 02/22] RISC-V ELF Machine Definition

2018-02-04 Thread Michael Clark
Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index e8a515c..8e457fc 100644 ---

[Qemu-devel] [PATCH v4 01/22] RISC-V Maintainers

2018-02-04 Thread Michael Clark
Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian Koppelmann as RISC-V Maintainers. Signed-off-by: Michael Clark --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0f952d4..d607039 100644 ---

[Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support

2018-02-04 Thread Michael Clark
Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 375 + 2 files changed, 379 insertions(+), 3 deletions(-) create mode 100644

[Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler

2018-02-04 Thread Michael Clark
The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and

[Qemu-devel] [PATCH v4 12/22] RISC-V HART Array

2018-02-04 Thread Michael Clark
Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 insertions(+)

[Qemu-devel] [PATCH v4 20/22] SiFive Freedom E300 RISC-V Machine

2018-02-04 Thread Michael Clark
This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark --- hw/riscv/sifive_e300.c | 232 +

[Qemu-devel] [PATCH v4 13/22] SiFive RISC-V CLINT Block

2018-02-04 Thread Michael Clark
The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_clint.c | 312

[Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation

2018-02-04 Thread Michael Clark
Implementation of linux user emulation for RISC-V. Signed-off-by: Michael Clark --- linux-user/elfload.c | 22 +++ linux-user/main.c | 97 ++ linux-user/riscv/syscall_nr.h | 275 ++

[Qemu-devel] [PATCH v4 17/22] SiFive RISC-V UART Device

2018-02-04 Thread Michael Clark
QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in

[Qemu-devel] [PATCH v4 22/22] RISC-V Build Infrastructure

2018-02-04 Thread Michael Clark
This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'

[Qemu-devel] [PATCH v4 15/22] RISC-V Spike Machines

2018-02-04 Thread Michael Clark
RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Signed-off-by:

[Qemu-devel] [PATCH v4 18/22] SiFive RISC-V PRCI Block

2018-02-04 Thread Michael Clark
Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 95 ++ include/hw/riscv/sifive_prci.h | 43 +++ 2

Re: [Qemu-devel] [PATCH 00/24] re-factor and add fp16 using glibc soft-fp

2018-02-04 Thread Howard Spoelstra
On Sun, Feb 4, 2018 at 5:11 AM, Richard Henderson wrote: > As discussed on list, the structure and inline function solution that > Alex and I have been writing from scratch introduces a sizeable > performance regression. Alex and I have done some work earlier > in

Re: [Qemu-devel] [PATCH 2/2] tests: Enable boot-serial-test for hppa

2018-02-04 Thread Thomas Huth
On 04.02.2018 07:49, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tests/boot-serial-test.c | 1 + > tests/Makefile.include | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c >