[Qemu-devel] [PATCH] linux-user: Implement setsockopt SOL_SOCKET/SO_LINGER

2018-02-05 Thread Andreas Schwab
Signed-off-by: Andreas Schwab --- linux-user/syscall.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index ff89016adc..82848fd97d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3130,6

[Qemu-devel] [PATCH 0/4] Misc VNC fixes / sanity checks

2018-02-05 Thread Daniel P . Berrangé
A few VNC changes suggested by Laszlo when reviewing my recent VNC patches Daniel P. Berrangé (4): ui: avoid risk of 32-bit int overflow in VNC buffer check ui: avoid 'local_err' variable shadowing in VNC SASL auth ui: check VNC audio frequency limit at time of reading from client ui:

[Qemu-devel] [PATCH 1/4] ui: avoid risk of 32-bit int overflow in VNC buffer check

2018-02-05 Thread Daniel P . Berrangé
For very large framebuffers, it is theoretically possible for the result of 'vs->throttle_output_offset * VNC_THROTTLE_OUTPUT_LIMIT_SCALE' to exceed the size of a 32-bit int. For this to happen in practice, the video RAM would have to be set to a large enough value, which is not likely today. None

Re: [Qemu-devel] [PATCH v2 5/6] qapi: add block-dirty-bitmap-merge

2018-02-05 Thread Vladimir Sementsov-Ogievskiy
03.02.2018 19:06, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 38 ++ include/block/dirty-bitmap.h | 2

Re: [Qemu-devel] [PULL 15/18] migration: split common postcopy out of ram postcopy

2018-02-05 Thread Vladimir Sementsov-Ogievskiy
05.02.2018 12:49, Greg Kurz wrote: On Fri, 22 Sep 2017 14:25:02 +0200 Juan Quintela wrote: From: Vladimir Sementsov-Ogievskiy Split common postcopy staff from ram postcopy staff. Signed-off-by: Vladimir Sementsov-Ogievskiy

Re: [Qemu-devel] [RFC 0/2] virtio-vhost-user: add virtio-vhost-user device

2018-02-05 Thread Wang, Wei W
On Friday, February 2, 2018 11:26 PM, Stefan Hajnoczi wrote: > On Tue, Jan 30, 2018 at 08:09:19PM +0800, Wei Wang wrote: > > Background: > > The vhost-user negotiation is split into 2 phases currently. The 1st > > phase happens when the connection is established, and we can find > > what's done in

Re: [Qemu-devel] [PATCH v3 06/12] vl: drop no_quit variable

2018-02-05 Thread Gerd Hoffmann
On Fri, Feb 02, 2018 at 09:35:52AM -0600, Eric Blake wrote: > On 02/02/2018 05:10 AM, Gerd Hoffmann wrote: > > Not used any more, delete it. > > > > Signed-off-by: Gerd Hoffmann > > --- > > vl.c | 7 ++- > > 1 file changed, 2 insertions(+), 5 deletions(-) > > > > diff

[Qemu-devel] [PULL 2/4] docs: add pvrdma device documentation.

2018-02-05 Thread Marcel Apfelbaum
Signed-off-by: Marcel Apfelbaum Signed-off-by: Yuval Shaia Reviewed-by: Shamir Rabinovitch --- docs/pvrdma.txt | 255 1 file changed, 255 insertions(+) create

[Qemu-devel] [PULL 1/4] mem: add share parameter to memory-backend-ram

2018-02-05 Thread Marcel Apfelbaum
Currently only file backed memory backend can be created with a "share" flag in order to allow sharing guest RAM with other processes in the host. Add the "share" flag also to RAM Memory Backend in order to allow remapping parts of the guest RAM to different host virtual addresses. This is needed

[Qemu-devel] [PULL 0/4] RDMA patches

2018-02-05 Thread Marcel Apfelbaum
The following changes since commit f24ee107a07f093bd7ed475dd48d7ba57ea3d8fe: Merge remote-tracking branch 'remotes/kraxel/tags/ui-20180202-pull-request' into staging (2018-02-02 18:54:11 +) are available in the git repository at: https://github.com/marcel-apf/qemu

[Qemu-devel] [PULL 4/4] MAINTAINERS: add entry for hw/rdma

2018-02-05 Thread Marcel Apfelbaum
Signed-off-by: Marcel Apfelbaum Signed-off-by: Yuval Shaia --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0f952d46ce..3e34ae25ea 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1995,6 +1995,14

Re: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread no-reply
Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180205102935.14736-1-da...@redhat.com Subject: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility === TEST SCRIPT BEGIN ===

[Qemu-devel] [PATCH 4/8] hw/intc/armv7m_nvic: Implement v8M CPPWR register

2018-02-05 Thread Peter Maydell
The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no

Re: [Qemu-devel] can not post bugs, launchpad error

2018-02-05 Thread Dr. David Alan Gilbert
* Toomas Soome (tso...@me.com) wrote: > hi! > > the bugtracker is quite unusable (has been for over an week), thats the error > from login: > > Oops! > Sorry, something just went wrong in Launchpad. > We’ve recorded what happened, and we’ll fix it as soon as possible. Apologies > for the

Re: [Qemu-devel] [PATCH v3 2/2] README: Document 'git-publish' workflow

2018-02-05 Thread Marc-André Lureau
On Mon, Feb 5, 2018 at 6:47 AM, Fam Zheng wrote: > Signed-off-by: Fam Zheng Looks good, thanks, Reviewed-by: Marc-André Lureau > --- > README | 30 +- > 1 file changed, 29 insertions(+), 1 deletion(-)

[Qemu-devel] [PATCH 1/8] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC

2018-02-05 Thread Peter Maydell
Instead of hardcoding the values of M profile ID registers in the NVIC, use the fields in the CPU struct. This will allow us to give different M profile CPU types different ID register values. This commit includes the addition of the missing ID_ISAR5, which exists as RES0 in both v7M and v8M.

[Qemu-devel] [PATCH 6/8] hw/intc/armv7m_nvic: Implement SCR

2018-02-05 Thread Peter Maydell
We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h

[Qemu-devel] [PATCH 8/8] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions

2018-02-05 Thread Peter Maydell
In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR, NVIC_ISER, NVIC_ICPR, NVIC_ICER, NVIC_IABR -- in all these cases we

[Qemu-devel] [PATCH 3/8] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops

2018-02-05 Thread Peter Maydell
For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them.

[Qemu-devel] [PATCH 2/8] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling

2018-02-05 Thread Peter Maydell
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs.

Re: [Qemu-devel] [PATCH v11 15/20] target/arm: Use vector infrastructure for aa64 constant shifts

2018-02-05 Thread Peter Maydell
On 26 January 2018 at 04:57, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/arm/translate-a64.c | 423 > + > 1 file changed, 350 insertions(+), 73 deletions(-)

Re: [Qemu-devel] [PATCH v5 1/6] machine: Convert the valid cpu types to use cpu_model

2018-02-05 Thread Igor Mammedov
On Fri, 2 Feb 2018 16:23:26 -0200 Eduardo Habkost wrote: > On Thu, Feb 01, 2018 at 04:42:05PM -0800, Alistair Francis wrote: > > As cpu_type is not a user visible string let's convert the > > valid_cpu_types to compare against cpu_model instead. This way we have a > > user

Re: [Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation

2018-02-05 Thread Andreas Schwab
On Feb 05 2018, Michael Clark wrote: > diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h > new file mode 100644 > index 000..bd164ef > --- /dev/null > +++ b/linux-user/riscv/syscall_nr.h > @@ -0,0 +1,275 @@ > +/* > + * Syscall numbers from

[Qemu-devel] [PATCH] linux-user: Implement copy_file_range

2018-02-05 Thread Andreas Schwab
No attempt is made to emulate it on the host. Signed-off-by: Andreas Schwab --- linux-user/syscall.c | 39 +++ 1 file changed, 39 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 07fb8de921..ff89016adc 100644 ---

Re: [Qemu-devel] [PATCH v3 1/1] s390x/cpu: expose the guest crash information

2018-02-05 Thread Cornelia Huck
On Fri, 2 Feb 2018 14:37:46 + Christian Borntraeger wrote: > This patch is the s390 implementation of guest crash information, > similar to commit d187e08dc4 ("i386/cpu: add crash-information QOM > property") and the related commits. We will detect several crash >

Re: [Qemu-devel] [PATCH 1/8] hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC

2018-02-05 Thread Philippe Mathieu-Daudé
On 02/05/2018 07:57 AM, Peter Maydell wrote: > Instead of hardcoding the values of M profile ID registers in the > NVIC, use the fields in the CPU struct. This will allow us to > give different M profile CPU types different ID register values. > This commit includes the addition of the missing

Re: [Qemu-devel] [PULL 6/8] iotest 205: new test for qmp nbd-server-remove

2018-02-05 Thread Vladimir Sementsov-Ogievskiy
05.02.2018 12:24, Kevin Wolf wrote: Am 26.01.2018 um 17:04 hat Eric Blake geschrieben: From: Vladimir Sementsov-Ogievskiy Signed-off-by: Vladimir Sementsov-Ogievskiy Message-Id: <20180119135719.24745-6-vsement...@virtuozzo.com> [eblake:

[Qemu-devel] [PATCH] iotests: 205: support only raw format

2018-02-05 Thread Vladimir Sementsov-Ogievskiy
The test is about qmp interface to NBD server, so there no reasons to run it for various disk formats. Also it actually do not support luks format, so, disable all format except raw. Signed-off-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/205 | 2 +- 1 file

Re: [Qemu-devel] can not post bugs, launchpad error

2018-02-05 Thread Peter Maydell
On 5 February 2018 at 09:36, Toomas Soome wrote: > the bugtracker is quite unusable (has been for over an week), thats the error > from login: > > Oops! > Sorry, something just went wrong in Launchpad. > We’ve recorded what happened, and we’ll fix it as soon as possible. Apologies

Re: [Qemu-devel] [PATCH] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread Christian Borntraeger
On 02/05/2018 10:34 AM, David Hildenbrand wrote: > On 05.02.2018 10:09, David Hildenbrand wrote: >> For now, the kernel does not properly indicate configured CPU subfunctions >> to the guest, but simply uses the host values (as support in KVM is still >> missing). That's why we missed to model

[Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread David Hildenbrand
For now, the kernel does not properly indicate configured CPU subfunctions to the guest, but simply uses the host values (as support in KVM is still missing). That's why we missed to model the PTFF subfunctions that come with Multiple-epoch facility. Let's properly add these, along with a new

[Qemu-devel] [Bug 1747393] [NEW] nvme is missing support for NVME_ADM_CMD_ASYNC_EV_REQ

2018-02-05 Thread Toomas Soome
Public bug reported: NVME_ADM_CMD_ASYNC_EV_REQ is required by specification but apparently we will be responded by error when this command is used. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml,

[Qemu-devel] [PATCH 5/8] hw/intc/armv7m_nvic: Implement cache ID registers

2018-02-05 Thread Peter Maydell
M profile cores have a similar setup for cache ID registers to A profile: * Cache Level ID Register (CLIDR) is a fixed value * Cache Type Register (CTR) is a fixed value * Cache Size ID Registers (CCSIDR) are a bank of registers; which one you see is selected by the Cache Size Selection

[Qemu-devel] [PATCH 7/8] target/arm: Implement writing to CONTROL_NS for v8M

2018-02-05 Thread Peter Maydell
In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Signed-off-by: Peter Maydell --- target/arm/helper.c | 10 ++ 1 file

[Qemu-devel] [PATCH 4/4] ui: extend VNC trottling tracing to SASL codepaths

2018-02-05 Thread Daniel P . Berrangé
In previous commit: commit 6aa22a29187e1908f5db738d27c64a9efc8d0bfa Author: Daniel P. Berrange Date: Mon Dec 18 19:12:27 2017 + ui: add trace events related to VNC client throttling trace points related to unthrottling client I/O were missed from the SASL

[Qemu-devel] [PATCH 3/4] ui: check VNC audio frequency limit at time of reading from client

2018-02-05 Thread Daniel P . Berrangé
The 'vs->as.freq' value is a signed integer, which is read from an unsigned 32-bit int field on the wire. There is thus a risk of overflow on 32-bit platforms. Move the frequency limit checking to be done at time of read before casting to a signed integer. Reported-by: Laszlo Ersek

Re: [Qemu-devel] [PATCH v2 3/6] qapi: add block-dirty-bitmap-enable/disable

2018-02-05 Thread Vladimir Sementsov-Ogievskiy
03.02.2018 19:09, Markus Armbruster wrote: Vladimir Sementsov-Ogievskiy writes: Signed-off-by: Vladimir Sementsov-Ogievskiy --- qapi/block-core.json | 42 ++ blockdev.c | 42

Re: [Qemu-devel] [PATCH v3 0/1] respin of s390 crash information

2018-02-05 Thread Cornelia Huck
On Fri, 2 Feb 2018 14:37:45 + Christian Borntraeger wrote: > This patch - originally from Jing Liu - was still on my disk and > somehow dropped of my attention. Here is a fixed up version. > It probably still needs some review and polish. > One open aspect is

Re: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread Cornelia Huck
On Mon, 5 Feb 2018 12:27:33 +0100 David Hildenbrand wrote: > On 05.02.2018 12:22, Christian Borntraeger wrote: > > Looks sane on a z14. > > Tested-by: Christian Borntraeger > > > > > > On 02/05/2018 11:29 AM, David Hildenbrand wrote: > >> ---

Re: [Qemu-devel] [PULL 15/18] migration: split common postcopy out of ram postcopy

2018-02-05 Thread Greg Kurz
On Fri, 22 Sep 2017 14:25:02 +0200 Juan Quintela wrote: > From: Vladimir Sementsov-Ogievskiy > > Split common postcopy staff from ram postcopy staff. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > Reviewed-by: Dr.

Re: [Qemu-devel] [PATCH v3 1/2] Add a git-publish configuration file

2018-02-05 Thread Marc-André Lureau
Hi On Mon, Feb 5, 2018 at 6:47 AM, Fam Zheng wrote: > git-publish [1] is a convenient tool to send patches and has been > popular among QEMU developers. Recently it has been made available in > Fedora official repo thanks to Stefan's work. > > One nice feature of the tool is a

Re: [Qemu-devel] [PATCH 4/6] target/arm: Add "-cpu max" support

2018-02-05 Thread Igor Mammedov
On Fri, 2 Feb 2018 17:54:43 + Peter Maydell wrote: > On 26 January 2018 at 15:44, Philippe Mathieu-Daudé wrote: > > On 01/26/2018 11:33 AM, Peter Maydell wrote: > >> On 26 January 2018 at 14:29, Philippe Mathieu-Daudé > >>

[Qemu-devel] [PATCH 0/8] v8m: minor missing regs and bugfixes

2018-02-05 Thread Peter Maydell
This patchset is the result of comparing the registers listed in the v8M Arm ARM against what QEMU was implementing. It adds a collection of generally unexciting missing registers (most of which we can simply NOP or make reads-as-written). There are also a couple of bug fixes in there, of which

Re: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread Christian Borntraeger
Looks sane on a z14. Tested-by: Christian Borntraeger On 02/05/2018 11:29 AM, David Hildenbrand wrote: > --- a/target/s390x/kvm.c > +++ b/target/s390x/kvm.c > @@ -2221,6 +2221,14 @@ void kvm_s390_get_host_cpu_model(S390CPUModel *model, > Error **errp) > return;

Re: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread David Hildenbrand
On 05.02.2018 12:22, Christian Borntraeger wrote: > Looks sane on a z14. > Tested-by: Christian Borntraeger > > > On 02/05/2018 11:29 AM, David Hildenbrand wrote: >> --- a/target/s390x/kvm.c >> +++ b/target/s390x/kvm.c >> @@ -2221,6 +2221,14 @@ void

[Qemu-devel] [PATCH 2/4] ui: avoid 'local_err' variable shadowing in VNC SASL auth

2018-02-05 Thread Daniel P . Berrangé
The start_auth_sasl() method declares a 'Error *local_err' variable in an inner if () {...} scope, which shadows a variable of the same name declared at the start of the method. This is confusing for reviewers and may trigger compiler warnings. Reported-by: Laszlo Ersek

Re: [Qemu-devel] [PATCH v2 1/1] virtio-balloon: include statistics of disk/file caches

2018-02-05 Thread Tomáš Golembiovský
ping On Tue, 5 Dec 2017 13:14:46 +0100 Tomáš Golembiovský wrote: > Signed-off-by: Tomáš Golembiovský > --- > hw/virtio/virtio-balloon.c | 1 + > include/standard-headers/linux/virtio_balloon.h | 3 ++- > 2 files changed, 3

Re: [Qemu-devel] [PATCH v2] s390x/cpumodel: model PTFF subfunctions for Multiple-epoch facility

2018-02-05 Thread David Hildenbrand
On 05.02.2018 13:22, Cornelia Huck wrote: > On Mon, 5 Feb 2018 12:27:33 +0100 > David Hildenbrand wrote: > >> On 05.02.2018 12:22, Christian Borntraeger wrote: >>> Looks sane on a z14. >>> Tested-by: Christian Borntraeger >>> >>> >>> On 02/05/2018 11:29

[Qemu-devel] [Bug 1747056] Re: FreeDOS / MS-Dos / Windows 3.11 cannot perform reboot with 'isapc' machine

2018-02-05 Thread Daniel Berrange
I bisected seabios and found this seabios change to be the cause of the problem commit b837e68d5a6c1a5945513f1995875445a1594c8a (refs/bisect/bad) Author: Kevin O'Connor Date: Mon Nov 9 15:00:19 2015 -0500 resume: Make KVM soft reboot loop detection more flexible

[Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers

2018-02-05 Thread Eric Auger
We introduce some helpers to handle wired IRQs and especially GERROR interrupt. SMMU writes GERROR register on GERROR event and SW acks GERROR interrupts by setting GERRORn. The Wired interrupts are edge sensitive hence the pulse usage. Signed-off-by: Eric Auger --- v7

[Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup

2018-02-05 Thread Eric Auger
We enumerate all the PCI devices attached to the SMMU and initialize an associated IOMMU memory region and address space. This happens on SMMU base instance init. Those info are stored in SMMUDevice objects. The devices are grouped according to the PCIBus they belong to. A hash table indexed by

[Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper

2018-02-05 Thread Eric Auger
Let's introduce a helper function aiming at recording an event in the event queue. Signed-off-by: Eric Auger --- v7 -> v8: - use dma_addr_t instead of hwaddr in smmuv3_record_event() - introduce struct SMMUEventInfo - add event_stringify + helpers for all fields ---

[Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk

2018-02-05 Thread Eric Auger
This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger --- v7 -> v8: - rework get_pte - use LOG_LEVEL_ERROR - remove error checking in get_block_pte_address - page table walk simplified (no VFIO replay anymore) - handle PTW error events - use

[Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton

2018-02-05 Thread Eric Auger
From: Prem Mallappa This patch implements a skeleton for the smmuv3 device. Datatypes and register definitions are introduced. The MMIO region, the interrupts and the queue are initialized. Only the MMIO read operation is implemented here. Signed-off-by: Prem

Re: [Qemu-devel] [PATCH RFC 05/21] qapi: Turn generators into modules

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > The next commit will introduce a common driver program for all > generators. The generators need to be modules for that. qapi2texi.py > already is. Make the other generators follow suit. > > The changes are actually

Re: [Qemu-devel] [PATCH RFC 09/21] qapi: Don't absolutize include file name in error messages

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Error messages print absolute filenames of included files even gave a > relative one on the command line: > > PYTHONPATH=scripts python -B tests/qapi-schema/test-qapi.py > tests/qapi-schema/include-cycle.json >

Re: [Qemu-devel] [PATCH v3 1/1] s390x/cpu: expose the guest crash information

2018-02-05 Thread Cornelia Huck
On Mon, 5 Feb 2018 14:44:36 +0100 Christian Borntraeger wrote: > On 02/05/2018 01:04 PM, Cornelia Huck wrote: > > > You're doing the crash_reason -> reason mapping here and also below. > > Maybe introduce a helper for it? > > > [] > >> diff --git

[Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type

2018-02-05 Thread Eric Auger
The new machine type exposes a new "iommu" virt machine option. The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3. Signed-off-by: Eric Auger --- v7 -> v8: - Revert to machine option, now dubbed "iommu", preparing for virtio instantiation. v5 -> v6:

Re: [Qemu-devel] [PATCH RFC 06/21] qapi-gen: New common driver for code and doc generators

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Whenever qapi-schema.json changes, we run six programs eleven times to > update eleven files. This is silly. Replace the six programs by a > single program that spits out all eleven files. > Now we will need

Re: [Qemu-devel] [PATCH RFC 16/21] qapi/types qapi/visit: Make visitors use QAPIGen more

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > The conversion is rather shallow so far: most of the output > accumulation is not converted. Take the next step: convert output > accumulation in QAPISchemaGenTypeVisitor and > QAPISchemaGenVisitVisitor. Helper

Re: [Qemu-devel] [PATCH 0/1] Fix unaligned reads in the tcg/tci.c

2018-02-05 Thread Anatoly Trosinenko
Ping. Patchwork link: http://patchwork.ozlabs.org/patch/866732/ Patchew link: http://patchew.org/QEMU/20180127134908.24095-1-anatoly.trosine...@gmail.com/ (Initially forgot to add Richard Henderson to CC.) 2018-01-27 16:49 GMT+03:00 Anatoly Trosinenko : > The code

[Qemu-devel] [PATCH v4] s390x/cpu: expose the guest crash information

2018-02-05 Thread Christian Borntraeger
This patch is the s390 implementation of guest crash information, similar to commit d187e08dc4 ("i386/cpu: add crash-information QOM property") and the related commits. We will detect several crash reasons, with the "disabled wait" being the most important one, since this is used by all s390

[Qemu-devel] virtio-blk discard support

2018-02-05 Thread Cathy Avery
Hi, I am looking at extending virtio-blk by adding support for the discard request. https://lists.nongnu.org/archive/html/qemu-devel/2018-01/msg03889.html My understanding is that you have already begun this work with [PATCH] virtio-blk: add DISCARD support to virtio-blk drive

Re: [Qemu-devel] [PATCH RFC 19/21] qapi/types: Generate separate .h, .c for each module

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Our qapi-schema.json is composed of modules connected by include > directives, but the generated code is monolithic all the same: one > qapi-types.h with all the types, one qapi-visit.h with all the > visitors, and so

Re: [Qemu-devel] [PATCH 01/10] cuda: do not use old_mmio accesses

2018-02-05 Thread Laurent Vivier
On 03/02/2018 11:37, Mark Cave-Ayland wrote: > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/macio/cuda.c | 40 > 1 file changed, 8 insertions(+), 32 deletions(-) > > diff --git a/hw/misc/macio/cuda.c

Re: [Qemu-devel] [PATCH 02/10] cuda: don't allow writes to port output pins

2018-02-05 Thread Laurent Vivier
On 03/02/2018 11:37, Mark Cave-Ayland wrote: > Use the direction registers as a mask to ensure that only input pins are > updated upon write. > > Signed-off-by: Mark Cave-Ayland > --- > hw/misc/macio/cuda.c | 4 ++-- > 1 file changed, 2 insertions(+), 2

[Qemu-devel] [PATCH v4 04/39] qcow2: Remove BDS parameter from qcow2_cache_get_table_idx()

2018-02-05 Thread Alberto Garcia
This function was only using the BlockDriverState parameter to get the cache table size (since it was equal to the cluster size). This is no longer necessary so this parameter can be removed. Signed-off-by: Alberto Garcia Reviewed-by: Eric Blake Reviewed-by:

Re: [Qemu-devel] [PULL 15/18] migration: split common postcopy out of ram postcopy

2018-02-05 Thread Greg Kurz
On Mon, 5 Feb 2018 15:11:10 +0300 Vladimir Sementsov-Ogievskiy wrote: > 05.02.2018 12:49, Greg Kurz wrote: > > On Fri, 22 Sep 2017 14:25:02 +0200 > > Juan Quintela wrote: > > > >> From: Vladimir Sementsov-Ogievskiy > >>

Re: [Qemu-devel] [PATCH 2/4] ui: avoid 'local_err' variable shadowing in VNC SASL auth

2018-02-05 Thread Laszlo Ersek
On 02/05/18 12:49, Daniel P. Berrangé wrote: > The start_auth_sasl() method declares a 'Error *local_err' variable in > an inner if () {...} scope, which shadows a variable of the same name > declared at the start of the method. This is confusing for reviewers and > may trigger compiler warnings.

[Qemu-devel] [PATCH] sdl: restore optimized redraw

2018-02-05 Thread Anatoly Trosinenko
The documentation on SDL_RenderPresent function states that "the backbuffer should be considered invalidated after each present", so copy the entire texture on each redraw. On the other hand, SDL_UpdateTexture function is described as "fairly slow function", so restrict it to just the changed

[Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support

2018-02-05 Thread Eric Auger
This series implements the emulation code for ARM SMMUv3. SMMUv3 gets instantiated by adding ",iommu=smmuv3" to the virt machine option. VHOST integration will be handled in a separate series. VFIO integration is not targeted at the moment. Only stage 1 and AArch64 page table walk are supported.

[Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers

2018-02-05 Thread Eric Auger
We introduce helpers to read/write into the command and event circular queues. smmuv3_write_eventq and smmuv3_cmq_consume will become static in subsequent patches. Invalidation commands are not yet dealt with. We do not cache data that need to be invalidated. This will change with vhost

[Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations

2018-02-05 Thread Eric Auger
Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger --- v7 -> v8: - precise in the commit message invalidation commands are not yet treated. - use new queue helpers - do not decode unhandled

Re: [Qemu-devel] [PATCH RFC 11/21] qapi: Lift error reporting from QAPISchema.__init__() to callers

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Signed-off-by: Markus Armbruster Reviewed-by: Marc-André Lureau > --- > scripts/qapi-gen.py| 8 ++-- > scripts/qapi/common.py | 23

[Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case

2018-02-05 Thread Eric Auger
At the moment, the SMMUv3 does not support notification on TLB invalidation. So let's abort as soon as such notifier gets enabled. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/smmuv3.c

[Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback

2018-02-05 Thread Eric Auger
This patch implements the IOMMU Memory Region translate() callback. Most of the code relates to the translation configuration decoding and check (STE, CD). Signed-off-by: Eric Auger --- v7 -> v8: - use address_space_rw - s/Ste/STE, s/Cd/CD - use dma_memory_read - remove

Re: [Qemu-devel] [PATCH RFC 20/21] Include less of qapi-types.h

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > In my "build everything" tree, a change to the types in > qapi-schema.json triggers a recompile of about 4500 out of 4800 > objects. > > The previous commit split up the generated qapi-types.h. Replace > includes of

Re: [Qemu-devel] [PATCH RFC 03/21] qapi: New classes QAPIGenC, QAPIGenH, QAPIGenDoc

2018-02-05 Thread Marc-Andre Lureau
Hi On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > These classes encapsulate accumulating and writing output. > > Convert C code generation to QAPIGenC and QAPIGenH. The conversion is > rather shallow: most of the output accumulation is not converted. > Left for

Re: [Qemu-devel] [PATCH RFC 13/21] qapi: Record 'include' directives in parse tree

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > The parse tree is a list of expressions. Except include expressions > currently get replaced by the included file's parse tree. > > Instead of throwing away the include expression, keep it with the file > name expanded

Re: [Qemu-devel] [PATCH RFC 04/21] qapi: Reduce use of global variables in generators some

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > In preparation of the next commit, which will turn the generators into > modules. These global variables will become local to main() then. > > Signed-off-by: Markus Armbruster Reviewed-by:

Re: [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

2018-02-05 Thread Richard Henderson
On 02/04/2018 10:22 PM, Michael Clark wrote: > Add CPU state header, CPU definitions and initialization routines > > Signed-off-by: Michael Clark > --- > target/riscv/cpu.c | 385 > target/riscv/cpu.h | 256

Re: [Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation

2018-02-05 Thread Richard Henderson
On 02/04/2018 10:22 PM, Michael Clark wrote: > TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU > RISC-V code generator has complete coverage for the Base ISA v2.2, > Privileged ISA v1.9.1 and Privileged ISA v1.10: > > - RISC-V Instruction Set Manual Volume I: User-Level ISA

Re: [Qemu-devel] [PATCH RFC 17/21] qapi/types qapi/visit: Generate built-in stuff into separate files

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Linking code from multiple separate QAPI schemata into the same > program is possible, but involves some weirdness around built-in > types: > > * We generate code for built-in types into .c only with option >

Re: [Qemu-devel] [PATCH RFC 14/21] qapi: Generate in source order

2018-02-05 Thread Markus Armbruster
Marc-Andre Lureau writes: > On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: >> The generators' conversion to visitors (merge commit 9e72681d16) >> changed the processing order of entities from source order to >> alphabetical order. The next

[Qemu-devel] [PATCH v4 05/39] qcow2: Remove BDS parameter from qcow2_cache_table_release()

2018-02-05 Thread Alberto Garcia
This function was only using the BlockDriverState parameter to get the cache table size (since it was equal to the cluster size). This is no longer necessary so this parameter can be removed. Signed-off-by: Alberto Garcia Reviewed-by: Eric Blake Reviewed-by:

Re: [Qemu-devel] [PATCH v3 0/2] Add git-publish config file

2018-02-05 Thread Stefan Hajnoczi
On Mon, Feb 05, 2018 at 01:47:23PM +0800, Fam Zheng wrote: > v3: Fix trivial hunk placement. [Michael] > Fix PPC sub-list. [Michael] > > v2: Add README paragraph [Marc-André, Stefan] > Fix 'trivial' profile [Marc-André] > Rename profiles [Stefan] > > Fam Zheng (2): > Add a

[Qemu-devel] [PATCH v4 20/39] qcow2: Update qcow2_get_cluster_offset() to support L2 slices

2018-02-05 Thread Alberto Garcia
qcow2_get_cluster_offset() checks how many contiguous bytes are available at a given offset. The returned number of bytes is limited by the amount that can be addressed without having to load more than one L2 table. Since we'll be loading L2 slices instead of full tables this patch changes the

[Qemu-devel] [PATCH v4 35/39] qcow2: Rename l2_table in count_cow_clusters()

2018-02-05 Thread Alberto Garcia
This function doesn't need any changes to support L2 slices, but since it's now dealing with slices intead of full tables, the l2_table variable is renamed for clarity. Signed-off-by: Alberto Garcia Reviewed-by: Eric Blake Reviewed-by: Max Reitz

Re: [Qemu-devel] [PATCH 1/4] ui: avoid risk of 32-bit int overflow in VNC buffer check

2018-02-05 Thread Laszlo Ersek
On 02/05/18 12:49, Daniel P. Berrangé wrote: > For very large framebuffers, it is theoretically possible for the result > of 'vs->throttle_output_offset * VNC_THROTTLE_OUTPUT_LIMIT_SCALE' to > exceed the size of a 32-bit int. For this to happen in practice, the > video RAM would have to be set to

Re: [Qemu-devel] [PATCH 3/4] ui: check VNC audio frequency limit at time of reading from client

2018-02-05 Thread Laszlo Ersek
On 02/05/18 12:49, Daniel P. Berrangé wrote: > The 'vs->as.freq' value is a signed integer, which is read from an > unsigned 32-bit int field on the wire. There is thus a risk of overflow > on 32-bit platforms. Move the frequency limit checking to be done at > time of read before casting to a

Re: [Qemu-devel] [PULL 15/18] migration: split common postcopy out of ram postcopy

2018-02-05 Thread Dr. David Alan Gilbert
* Greg Kurz (gr...@kaod.org) wrote: > On Fri, 22 Sep 2017 14:25:02 +0200 > Juan Quintela wrote: > > > From: Vladimir Sementsov-Ogievskiy > > > > /* Sent prior to starting the destination running in postcopy, discard > > pages > > @@ -1354,6

[Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes

2018-02-05 Thread Eric Auger
The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger Signed-off-by: Prem Mallappa ---

[Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board

2018-02-05 Thread Eric Auger
From: Prem Mallappa Add code to instantiate an smmuv3 in virt machine. A new iommu integer member is introduced in VirtMachineState to store the type of the iommu in use. Signed-off-by: Prem Mallappa Signed-off-by: Eric Auger

Re: [Qemu-devel] [PATCH RFC 14/21] qapi: Generate in source order

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > The generators' conversion to visitors (merge commit 9e72681d16) > changed the processing order of entities from source order to > alphabetical order. The next commit needs source order, so change it > back. > >

[Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route

2018-02-05 Thread Eric Auger
In case the MSI is translated by an IOMMU we need to fixup the MSI route with the translated address. Signed-off-by: Eric Auger --- v5 -> v6: - use IOMMUMemoryRegionClass API It is still unclear to me if we need to register an IOMMUNotifier to handle any change in the

Re: [Qemu-devel] [PATCH RFC 02/21] qapi: Generate up-to-date copyright notice

2018-02-05 Thread Marc-Andre Lureau
Hi On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > Each generator carries a copyright notice for the generator itself, > and another one for the files it generates. Only the former have been > updated along the way, the latter have not, and are all out of date. > >

Re: [Qemu-devel] [PATCH RFC 15/21] qapi: Record 'include' directives in intermediate representation

2018-02-05 Thread Marc-Andre Lureau
On Fri, Feb 2, 2018 at 2:03 PM, Markus Armbruster wrote: > The include directive permits modular QAPI schemata, but the generated > code is monolithic all the same. To permit generating modular code, > the front end needs to pass more information on inclusions to the back >

Re: [Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers

2018-02-05 Thread Richard Henderson
On 02/04/2018 10:22 PM, Michael Clark wrote: > Privileged control and status register helpers and page fault handling. > > Signed-off-by: Michael Clark > --- > target/riscv/helper.c| 464 ++ > target/riscv/helper.h| 78 ++ >

Re: [Qemu-devel] [PATCH v4 22/22] RISC-V Build Infrastructure

2018-02-05 Thread Richard Henderson
On 02/04/2018 10:22 PM, Michael Clark wrote: > This adds RISC-V into the build system enabling the following targets: > > - riscv32-softmmu > - riscv64-softmmu > - riscv32-linux-user > - riscv64-linux-user > > This adds defaults configs for RISC-V, enables the build for the RISC-V > CPU core,

[Qemu-devel] [PATCH v4 13/39] qcow2: Add l2_slice_size field to BDRVQcow2State

2018-02-05 Thread Alberto Garcia
The BDRVQcow2State structure contains an l2_size field, which stores the number of 64-bit entries in an L2 table. For efficiency reasons we want to be able to load slices instead of full L2 tables, so we need to know how many entries an L2 slice can hold. An L2 slice is the portion of an L2

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