[Qemu-devel] [PATCH 0/2] qmp: add query-cpus-fast

We've recently debugged a huge performance degradation we were getting on a latency sensitive workload down to the fact that libvirt is issuing query-cpus. As it turns out, query-cpus always interrupts all vCPU threads so that they can run ioctl to collect a number of register information, most

[Qemu-devel] [PATCH 2/2] qmp: document query-cpus performance issue

Signed-off-by: Luiz Capitulino --- qapi-schema.json | 4 1 file changed, 4 insertions(+) diff --git a/qapi-schema.json b/qapi-schema.json index 82d6f12b53..0665a14dba 100644 --- a/qapi-schema.json +++ b/qapi-schema.json @@ -526,6 +526,10 @@ # # Returns a list of

[Qemu-devel] [PATCH 1/2] qmp: add query-cpus-fast

The query-cpus command has an extremely serious side effect: it always interrupt all running vCPUs so that they can run ioctl calls. This can cause a huge performance degradation for some workloads. And most of the information retrieved by the ioctl calls are not even used by query-cpus. This

Re: [Qemu-devel] [PATCH v6] s390x/cpu: expose the guest crash information

On 02/07/2018 10:58 AM, Cornelia Huck wrote: On Wed, 7 Feb 2018 12:38:33 + Christian Borntraeger wrote: This patch is the s390 implementation of guest crash information, similar to commit d187e08dc4 ("i386/cpu: add crash-information QOM property") and the related

Re: [Qemu-devel] [PATCH v9 02/16] sdhci: add qtest to check the SD capabilities register

On 02/07/2018 02:10 PM, Paolo Bonzini wrote: > On 23/01/2018 03:08, Philippe Mathieu-Daudé wrote: >> The PCI model is tested with the pc/x86_64 machine, >> the SysBus model with the smdkc210/arm machine. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> tests/sdhci-test.c

Re: [Qemu-devel] [PULL 00/14] Error reporting patches for 2018-02-06

On 6 February 2018 at 19:50, Markus Armbruster wrote: > The following changes since commit 20e0d439a6ded635ec89f6135c08cd5541c68962: > > Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20180204' into > staging (2018-02-06 14:21:41 +) > > are available in the git

Re: [Qemu-devel] [virtio-dev] Re: [PATCH v1 6/6] vhost-user: add VFIO based accelerators support

On Wed, Feb 7, 2018 at 8:43 AM, Michael S. Tsirkin wrote: > On Sun, Feb 04, 2018 at 01:49:46PM -0800, Alexander Duyck wrote: >> On Thu, Jan 25, 2018 at 9:57 PM, Tiwei Bie wrote: >> > On Fri, Jan 26, 2018 at 11:41:27AM +0800, Jason Wang wrote: >> >> On

Re: [Qemu-devel] [PATCH v2 7/8] migration/ram: ensure write persistence on loading compressed pages to PMEM

On Wed, Feb 7, 2018 at 5:24 AM, Dr. David Alan Gilbert wrote: > * Haozhong Zhang (haozhong.zh...@intel.com) wrote: >> On 02/07/18 13:03 +, Dr. David Alan Gilbert wrote: >> > * Haozhong Zhang (haozhong.zh...@intel.com) wrote: >> > > On 02/07/18 11:54 +, Dr. David Alan

Re: [Qemu-devel] [PATCH v7 26/26] qmp: add query-sev-launch-measure command

On 02/07/2018 10:29 AM, Eric Blake wrote: ... +# +# Since: 2.12 +# +# Notes: If measurement is not available then a null measurement is returned. Null measurement, as in empty string?  Would it be better to have query-sev-launch-measure return an error instead of an SevLaunchMeasureInfo

[Qemu-devel] [PATCH v10 04/16] sdhci: add a check_capab_baseclock() qtest

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index e961f2b997..45caf66455 100644 ---

[Qemu-devel] [PATCH v10 16/16] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet

checking Xilinx datasheet "UG585" (v1.12.1) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/xilinx_zynq.c | 53 tests/sdhci-test.c | 5 + 2 files changed, 34

[Qemu-devel] [PATCH v10 10/16] sdhci: check the Spec v1 capabilities correctness

Incorrect value will throw an error. Note than Spec v2 is supported by default. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 21 ++- hw/sd/sdhci.c | 97

[Qemu-devel] [PATCH v10 00/16] SDHCI: clean v1/v2 Specs (part 2)

Patches missing review: 2 (PCI qtests) and 11 (trivial) Since v9: - replace global by struct QSDHCI in qtests (suggested by Paolo) (this generates changes in patches 3-6 but since they are only code adapted and no logical changes I kept Stefan R-b) - added Alistair R-b Since v8: - we keep

[Qemu-devel] [PATCH v10 01/16] sdhci: use error_propagate(local_err) in realize()

avoid the "errp && *errp" pattern (not recommended in "qapi/error.h" comments). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH v10 02/16] sdhci: add qtest to check the SD capabilities register

The PCI model is tested with the pc/x86_64 machine, the SysBus model with the smdkc210/arm machine. Signed-off-by: Philippe Mathieu-Daudé --- tests/sdhci-test.c | 139 + tests/Makefile.include | 3 ++ 2 files changed, 142

Re: [Qemu-devel] [PATCH 2/3] MAINTAINERS: reorganize s390-ccw bios maintainership

On 07.02.2018 16:55, Cornelia Huck wrote: > Split it out from the s390-ccw-virtio machine, add Thomas as a > maintainer in addition to Christian. > > Signed-off-by: Cornelia Huck > --- > MAINTAINERS | 11 +-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff

Re: [Qemu-devel] [RFC PATCH 18/34] hyperv: add support for KVM_HYPERV_EVENTFD

On Wed, Feb 07, 2018 at 12:01:41PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > When setting up a notifier for Hyper-V event connection, attempt to use > > the KVM-assisted one first, and fall back to userspace handling of the > > hypercall if the kernel doesn't

Re: [Qemu-devel] [RFC PATCH 33/34] vmbus: add support for rom files

On Wed, Feb 07, 2018 at 12:18:38PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > In order to leverage third-party drivers for VMBus devices in firmware > > (in particular, there's a case with iPXE driver for hv-net in SeaBIOS > > and OVMF), introduce an infrastructure

Re: [Qemu-devel] [RFC PATCH 21/34] vmbus: build configuration

On Wed, Feb 07, 2018 at 12:04:01PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > From: Evgeny Yakovlev > > > > Add option to configure and makefiles to enable building vmbus support > > (default to "on" on Linux and "off" otherwise). > >

[Qemu-devel] [PATCH v10 14/16] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64()

We only set a 32-bit value, but this is a good practice in case this code is used as reference. (missed in 5efc9016e52) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/exynos4210.c | 2 +- 1 file changed, 1

Re: [Qemu-devel] [PATCH v6] s390x/cpu: expose the guest crash information

On 02/07/2018 01:38 PM, Christian Borntraeger wrote: > --- a/vl.c > +++ b/vl.c > @@ -1738,7 +1738,7 @@ void qemu_system_reset(ShutdownCause reason) > > void qemu_system_guest_panicked(GuestPanicInformation *info) > { > -qemu_log_mask(LOG_GUEST_ERROR, "Guest crashed\n"); > +

Re: [Qemu-devel] [RFC PATCH 22/34] i386: Hyper-V VMBus ACPI DSDT entry

On Wed, Feb 07, 2018 at 12:05:23PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > From: Andrey Smetanin > > > > Guest OS uses ACPI to discover vmbus presence. Add a corresponding > > entry to DSDT in case vmbus has been enabled. > > > >

Re: [Qemu-devel] [RFC PATCH 27/34] tests: hv-scsi: add start-stop test

On Wed, Feb 07, 2018 at 12:15:50PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > +if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { > > +g_printerr("Hyper-V / VMBus are only available on x86\n"); > > +exit(EXIT_FAILURE); > > +} > > This

Re: [Qemu-devel] [PATCH v6] s390x/cpu: expose the guest crash information

On 02/07/2018 12:44 PM, Christian Borntraeger wrote: +} else if (info->type == GUEST_PANIC_INFORMATION_TYPE_S390) { +qemu_log_mask(LOG_GUEST_ERROR, " on cpu %d: %s\n" + "PSW: 0x%016" PRIx64 " 0x%016" PRIx64"\n", +

Re: [Qemu-devel] [RFC PATCH 12/34] hyperv: add synic event flag signaling

On Wed, Feb 07, 2018 at 11:58:58AM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > +/* > > + * Set given event flag for a given sint on a given vcpu, and signal the > > sint. > > + */ > > +int hyperv_set_evt_flag(HvSintRoute *sint_route, unsigned evtno) > > Any reason

Re: [Qemu-devel] [PATCH v10 00/16] SDHCI: clean v1/v2 Specs (part 2)

On Wed, Feb 7, 2018 at 10:19 AM, Philippe Mathieu-Daudé wrote: > Patches missing review: 2 (PCI qtests) and 11 (trivial) I don't see patch 11 on the list. I can see it in my Xilinx email as it was sent directly to that. I can't cleanly reply to it from my Xilinx Outlook account

Re: [Qemu-devel] [PATCH] Drop unneeded system header includes

On 07.02.2018 17:03, Eric Blake wrote: > is a non-standard obsolete header that was long ago > replaced by . > > is a non-standard header; it is not obsolete (we must > use it for malloc_trim, for example), but generally should not > be used in files that just need malloc() and friends, where >

Re: [Qemu-devel] [PATCH v1 1/2] timer: Initial commit of xlnx-pmu-iomod-pit device

On 02/07/2018 04:49 PM, Alistair Francis wrote: > On Tue, Feb 6, 2018 at 6:18 PM, Philippe Mathieu-Daudé > wrote: >> Hi Alistair, >> >> On 02/06/2018 07:23 PM, Alistair Francis wrote: >>> Signed-off-by: Alistair Francis >>> --- >>> >>>

[Qemu-devel] [PATCH v10 03/16] sdhci: add check_capab_readonly() qtest

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 24 1 file changed, 24 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 1105e07093..e961f2b997 100644 ---

[Qemu-devel] [PATCH v10 15/16] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2)

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/arm/exynos4210.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index d89322c7ea..06f9d1ffa4 100644 ---

Re: [Qemu-devel] [PATCH v7 05/26] target/i386: add memory encryption feature cpuid support

On 02/07/2018 10:54 AM, Paolo Bonzini wrote: On 07/02/2018 17:06, Brijesh Singh wrote: AMD EPYC processors support memory encryption feature. The feature is reported through CPUID 8000_001F[EAX]. Fn8000_001F [EAX]: Bit 0 Secure Memory Encryption (SME) supported Bit 1 Secure Encrypted

Re: [Qemu-devel] [RFC PATCH 08/34] hyperv: qom-ify SynIC

On Wed, Feb 07, 2018 at 11:45:28AM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > +static SynICState *get_synic(X86CPU *cpu) > > +{ > > +SynICState *synic = > > +SYNIC(object_resolve_path_component(OBJECT(cpu), "synic")); > > +assert(synic); > > +

[Qemu-devel] Throttling filter node status?

Hi Manos, I hope you're doing well and that you've had a good time at university after Google Summer of Code. Do you have time to work on getting the remainder of your GSoC work merged over the coming weeks? If not, don't feel bad but please let us know so someone can take over the patches.

Re: [Qemu-devel] [PATCH 1/2] qmp: add query-cpus-fast

On 02/07/2018 11:50 AM, Luiz Capitulino wrote: The query-cpus command has an extremely serious side effect: it always interrupt all running vCPUs so that they can run s/interrupt/interrupts/ ioctl calls. This can cause a huge performance degradation for some workloads. And most of the

Re: [Qemu-devel] [RFC PATCH 09/34] hyperv: block SynIC use in QEMU in incompatible configurations

On Wed, Feb 07, 2018 at 11:46:30AM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > Certain configurations do not allow SynIC to be used in QEMU. In > > particular, > > > > - when hyperv_vpindex is off, SINT routes can't be used as they refer to > > the destination

Re: [Qemu-devel] [RFC PATCH 11/34] hyperv: add synic message delivery

On Wed, Feb 07, 2018 at 11:58:08AM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > + > > +HvSintMsgCb msg_cb; > > +void *msg_cb_data; > > +struct hyperv_message *msg; > > +/* > > + * the state of the message staged in .msg: > > + * 0- the

Re: [Qemu-devel] [PULL 00/20] Miscellaneous patches for 2018-02-07

2018-02-07 12:39 GMT+00:00 Markus Armbruster : > The following changes since commit 20e0d439a6ded635ec89f6135c08cd5541c68962: > > Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20180204' into > staging (2018-02-06 14:21:41 +) > > are available in the git

Re: [Qemu-devel] [RFC PATCH 25/34] scsi: add Hyper-V/VMBus SCSI controller

On Wed, Feb 07, 2018 at 12:11:50PM +0100, Paolo Bonzini wrote: > On 06/02/2018 21:30, Roman Kagan wrote: > > +blk_io_plug(d->conf.blk); > > +if (scsi_req_enqueue(sreq)) { > > +scsi_req_continue(sreq); > > +} > > +blk_io_unplug(d->conf.blk); > > Is plug/unplug really

Re: [Qemu-devel] [PATCH v6] s390x/cpu: expose the guest crash information

On 02/07/2018 05:58 PM, Cornelia Huck wrote: > >> +## >> +# @S390CrashReason: >> +# >> +# Reason why the CPU is in a crashed state. >> +# >> +# @unknown: no crash reason was set >> +# >> +# @disabledwait: the CPU has entered a disabled wait state >> +# >> +# @extintloop: timer interrupt with

[Qemu-devel] [PATCH v10 13/16] sdhci: check Spec v2 capabilities (DMA and 64-bit bus)

Incorrect value will throw an error. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 14 +++--- hw/sd/sdhci.c | 19 +++ 2 files changed, 22 insertions(+), 11

[Qemu-devel] [PATCH v10 08/16] sdhci: use a numeric value for the default CAPAB register

using many #defines is not portable when scaling to different HCI. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci.c | 74 +-- 1 file changed, 16

[Qemu-devel] [PATCH v10 12/16] sdhci: Fix 64-bit ADMA2

From: Sai Pavan Boddu The 64-bit ADMA address is not converted to the cpu endianes correctly. This patch fixes the issue and uses a valid mask for the attribute data. Signed-off-by: Sai Pavan Boddu [AF: Re-write commit message] Reviewed-by: Alistair

[Qemu-devel] [PATCH v10 06/16] sdhci: add qtest to check the SD Spec version

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 24 1 file changed, 24 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 4b901b6cf1..ee12c4be7b 100644 ---

Re: [Qemu-devel] [PATCH 2/2] qmp: document query-cpus performance issue

On 02/07/2018 11:50 AM, Luiz Capitulino wrote: Signed-off-by: Luiz Capitulino --- qapi-schema.json | 4 1 file changed, 4 insertions(+) diff --git a/qapi-schema.json b/qapi-schema.json index 82d6f12b53..0665a14dba 100644 --- a/qapi-schema.json +++

Re: [Qemu-devel] [PATCH v2 7/8] migration/ram: ensure write persistence on loading compressed pages to PMEM

* Dan Williams (dan.j.willi...@intel.com) wrote: > On Wed, Feb 7, 2018 at 5:24 AM, Dr. David Alan Gilbert > wrote: > > * Haozhong Zhang (haozhong.zh...@intel.com) wrote: > >> On 02/07/18 13:03 +, Dr. David Alan Gilbert wrote: > >> > * Haozhong Zhang

[Qemu-devel] [PATCH v10 09/16] sdhci: simplify sdhci_get_fifolen()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 4 +++- hw/sd/sdhci.c | 20 +--- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/hw/sd/sdhci-internal.h

Re: [Qemu-devel] [qemu-s390x] [PATCH 1/3] MAINTAINERS: add myself as overall s390x maintainer

On 02/07/2018 04:55 PM, Cornelia Huck wrote: > All your mainframes are belong to me. > > Signed-off-by: Cornelia Huck Acked-by: Christian Borntraeger > --- > MAINTAINERS | 23 +++ > 1 file changed, 23 insertions(+) > > diff

[Qemu-devel] [PATCH v10 05/16] sdhci: add a check_capab_sdma() qtest

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 45caf66455..4b901b6cf1 100644 --- a/tests/sdhci-test.c

Re: [Qemu-devel] [qemu-s390x] [PATCH 2/3] MAINTAINERS: reorganize s390-ccw bios maintainership

On 02/07/2018 04:55 PM, Cornelia Huck wrote: > Split it out from the s390-ccw-virtio machine, add Thomas as a > maintainer in addition to Christian. > > Signed-off-by: Cornelia Huck Acked-by: Christian Borntraeger Thanks Thomas for volunteering to

Re: [Qemu-devel] Block Migration and CPU throttling

* Peter Lieven (p...@kamp.de) wrote: > Am 12.12.2017 um 18:05 schrieb Dr. David Alan Gilbert: > > * Peter Lieven (p...@kamp.de) wrote: > > > Am 21.09.2017 um 14:36 schrieb Dr. David Alan Gilbert: > > > > * Peter Lieven (p...@kamp.de) wrote: > > > > > Am 19.09.2017 um 16:41 schrieb Dr. David Alan

Re: [Qemu-devel] [PATCH 2/2] qmp: document query-cpus performance issue

On Wed, 7 Feb 2018 12:50:59 -0600 Eric Blake wrote: > On 02/07/2018 11:50 AM, Luiz Capitulino wrote: > > Signed-off-by: Luiz Capitulino > > --- > > qapi-schema.json | 4 > > 1 file changed, 4 insertions(+) > > > > diff --git a/qapi-schema.json

[Qemu-devel] [PATCH v10 07/16] sdhci: add a 'spec_version property' (default to v2)

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 4 ++-- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 27 +++ 3 files changed, 27 insertions(+), 6 deletions(-)

Re: [Qemu-devel] [PATCH v2 7/8] migration/ram: ensure write persistence on loading compressed pages to PMEM

On Wed, Feb 7, 2018 at 10:08 AM, Dr. David Alan Gilbert wrote: > * Dan Williams (dan.j.willi...@intel.com) wrote: >> On Wed, Feb 7, 2018 at 5:24 AM, Dr. David Alan Gilbert >> wrote: >> > * Haozhong Zhang (haozhong.zh...@intel.com) wrote: >> >> On

Re: [Qemu-devel] [PATCH v2 7/8] migration/ram: ensure write persistence on loading compressed pages to PMEM

* Dan Williams (dan.j.willi...@intel.com) wrote: > On Wed, Feb 7, 2018 at 10:08 AM, Dr. David Alan Gilbert > wrote: > > * Dan Williams (dan.j.willi...@intel.com) wrote: > >> On Wed, Feb 7, 2018 at 5:24 AM, Dr. David Alan Gilbert > >> wrote: > >> > *

Re: [Qemu-devel] [PATCH v1 1/2] timer: Initial commit of xlnx-pmu-iomod-pit device

On Tue, Feb 6, 2018 at 6:18 PM, Philippe Mathieu-Daudé wrote: > Hi Alistair, > > On 02/06/2018 07:23 PM, Alistair Francis wrote: >> Signed-off-by: Alistair Francis >> --- >> >> include/hw/timer/xlnx-pmu-iomod-pit.h | 58 >>

[Qemu-devel] [PATCH v1] Implement support for IEEE 754-201x minimumNumber/maximumNumber

QEMU currently implements IEEE 754-2008 minNum/maxNum. This patch adds support for IEEE 754-201x minimumNumber/maximumNumber which is required by the RISC-V port. minNum(x, y) is defined as - min(x, y) if neither is NaN - if one of x and y is a number and one is qNaN, return the number - if both

Re: [Qemu-devel] [PATCH] block: early check for blockers on drive-mirror

On Wed, 02/07 17:29, Paolo Bonzini wrote: > Even if an op blocker is present for BLOCK_OP_TYPE_MIRROR_SOURCE, > it is checked a bit late and the result is that the target is > created even if drive-mirror subsequently fails. Add an early > check to avoid this. > > Signed-off-by: Paolo Bonzini

[Qemu-devel] [PATCH v5 08/23] RISC-V GDB Stub

GDB Register read and write routines. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- target/riscv/gdbstub.c | 60 ++ 1 file changed, 60 insertions(+) create mode 100644

[Qemu-devel] [PATCH v5 23/23] RISC-V Build Infrastructure

This adds RISC-V into the build system enabling the following targets: - riscv32-softmmu - riscv64-softmmu - riscv32-linux-user - riscv64-linux-user This adds defaults configs for RISC-V, enables the build for the RISC-V CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'

[Qemu-devel] [PATCH v5 13/23] RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads. Signed-off-by: Michael Clark --- hw/riscv/riscv_hart.c | 95 +++ include/hw/riscv/riscv_hart.h | 45 2 files changed, 140 insertions(+)

[Qemu-devel] [PATCH v5 20/23] SiFive RISC-V Test Finisher

Test finisher memory mapped device used to exit simulation. Signed-off-by: Michael Clark --- hw/riscv/sifive_test.c | 99 ++ include/hw/riscv/sifive_test.h | 48 2 files changed, 147 insertions(+) create mode

[Qemu-devel] [PATCH v5 22/23] SiFive Freedom U500 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive U500 SDK. The following machine is implemented: - 'sifive_u500'; CLINT, PLIC, UART, device-tree Signed-off-by: Michael Clark --- hw/riscv/sifive_u500.c | 338 +

Re: [Qemu-devel] [PATCH 1/2] scsi: add unrealize method for SCSI devices

On Wed, 02/07 17:36, Paolo Bonzini wrote: > The next patch will introduce a different unrealize implementation > for scsi-block. Compared to the code before commit fb7b5c0df6 > ("scsi: devirtualize unrealize of SCSI devices", 2014-10-31), the > common code for all SCSI devices is kept in

Re: [Qemu-devel] [PATCH v4 03/22] RISC-V CPU Core Definition

On Wed, Feb 7, 2018 at 4:03 AM, Igor Mammedov wrote: > On Tue, 6 Feb 2018 11:09:56 +1300 > Michael Clark wrote: > > > On Tue, Feb 6, 2018 at 4:04 AM, Igor Mammedov > wrote: > > > > > On Mon, 5 Feb 2018 19:22:28 +1300 > > > Michael

Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 1518053328-34687-1-git-send-email-...@sifive.com Subject: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

[Qemu-devel] [PULL 05/16] coroutine-lock: make qemu_co_enter_next thread-safe

From: Paolo Bonzini qemu_co_queue_next does not need to release and re-acquire the mutex, because the queued coroutine does not run immediately. However, this does not hold for qemu_co_enter_next. Now that qemu_co_queue_wait can synchronize (via QemuLockable) with code

Re: [Qemu-devel] [virtio-dev] Re: [PATCH v1 6/6] vhost-user: add VFIO based accelerators support

On Wed, Feb 07, 2018 at 10:02:24AM -0800, Alexander Duyck wrote: > On Wed, Feb 7, 2018 at 8:43 AM, Michael S. Tsirkin wrote: > > On Sun, Feb 04, 2018 at 01:49:46PM -0800, Alexander Duyck wrote: > >> On Thu, Jan 25, 2018 at 9:57 PM, Tiwei Bie wrote: > >> > On

Re: [Qemu-devel] [PATCH v2 08/13] allow block_job_relax to return -ECANCELED

On 2018-01-19 21:58, John Snow wrote: > This is just an optimization for callers who are likely going to > want to check quite close to this call if the job was canceled or > not anyway. But jobs are “cancelled” and not “canceled”. !!! > > Along the same lines, add the return to

[Qemu-devel] [PULL 09/20] tcg: Add generic vector helpers with a scalar operand

Use dup to convert a non-constant scalar to a third vector. Add addition, multiplication, and logical operations with an immediate. Add addition, subtraction, multiplication, and logical operations with a non-constant scalar. Allow for the front-end to build operations in which the scalar

Re: [Qemu-devel] [RFC PATCH] vfio/pci: Add ioeventfd support

On 08/02/18 01:12, Alex Williamson wrote: > On Wed, 7 Feb 2018 15:48:26 +1100 > Alexey Kardashevskiy wrote: > >> On 07/02/18 15:25, Alex Williamson wrote: >>> On Wed, 7 Feb 2018 15:09:22 +1100 >>> Alexey Kardashevskiy wrote: On 07/02/18 11:08, Alex

[Qemu-devel] [PATCH v5 19/23] SiFive RISC-V PRCI Block

Simple model of the PRCI (Power, Reset, Clock, Interrupt) to emulate register reads made by the SDK BSP. Signed-off-by: Michael Clark --- hw/riscv/sifive_prci.c | 95 ++ include/hw/riscv/sifive_prci.h | 43 +++ 2

Re: [Qemu-devel] [PATCH 2/2] scsi: add block job opblockers for scsi-block

On Wed, 02/07 17:36, Paolo Bonzini wrote: > scsi-block bypasses the dirty bitmaps and pre-write notifiers, so it > cannot be the source of a block job. The gist of the fix is to add > op-blockers to the BlockBackend, and remove them at "unrealize" time, > but things are a little more complex

[Qemu-devel] [PATCH v5 15/23] SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a parameterizable interrupt controller based on SiFive's PLIC specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_plic.c | 554 +

[Qemu-devel] [PULL 14/16] docs: Add section for NVMe VFIO driver

Signed-off-by: Fam Zheng Reviewed-by: Stefan Hajnoczi Message-Id: <20180116060901.17413-9-f...@redhat.com> Signed-off-by: Fam Zheng --- docs/qemu-block-drivers.texi | 37 + qemu-doc.texi|

[Qemu-devel] [PULL 16/16] docs: Add docs/devel/testing.rst

To make our efforts on QEMU testing easier to consume by contributors, let's add a document. For example, Patchew reports build errors on patches that should be relatively easy to reproduce with a few steps, and it is much nicer if there is such a documentation that it can refer to. This focuses

[Qemu-devel] [PATCH v5 06/23] Softfloat support for IEEE 754-201x minimumNumber/maximumNumber

QEMU currently implements IEEE 754-2008 minNum/maxNum. This patch adds support for IEEE 754-201x minimumNumber/maximumNumber which is required by the RISC-V port. minNum(x, y) is defined as - min(x, y) if neither is NaN - if one of x and y is a number and one is qNaN, return the number - if both

[Qemu-devel] [PATCH v5 05/23] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Reviewed-by: Richard Henderson Signed-off-by: Michael Clark --- target/riscv/helper.c| 464 ++ target/riscv/helper.h| 78 ++

[Qemu-devel] [PATCH v5 17/23] RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO. The following machine is implemented: - 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree Signed-off-by: Michael Clark --- hw/riscv/virt.c | 375

[Qemu-devel] [PATCH v5 02/23] RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243 Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Michael Clark --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h

[Qemu-devel] [PATCH v5 21/23] SiFive Freedom E300 RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark --- hw/riscv/sifive_e300.c | 232 +

[Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation

TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU RISC-V code generator has complete coverage for the Base ISA v2.2, Privileged ISA v1.9.1 and Privileged ISA v1.10: - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2 - RISC-V Instruction Set Manual Volume II:

Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

We are now passing all but one of the set of tests cases in riscv-tests. The one failing set of tests relates to support for "9.2 NaN Boxing of Narrower Values" as per the RISC-V ISA Specification v2.2. The remaining case is where we try to use a single-precision operation on an input that doesn't

[Qemu-devel] [PULL 08/16] util: Introduce vfio helpers

This is a library to manage the host vfio interface, which could be used to implement userspace device driver code in QEMU such as NVMe or net controllers. Signed-off-by: Fam Zheng Reviewed-by: Stefan Hajnoczi Message-Id:

[Qemu-devel] [PULL 07/16] stubs: Add stubs for ram block API

These functions will be wanted by block-obj-y but the actual definition is in obj-y, so stub them to keep the linker happy. Signed-off-by: Fam Zheng Acked-by: Paolo Bonzini Message-Id: <20180110091846.10699-2-f...@redhat.com> Reviewed-by: Stefan Hajnoczi

Re: [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support

> On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote: > > From: Chao Peng > > > > Expose Intel Processor Trace feature to guest. > > > > To make Intel PT live migration safe and get same CPUID information > > with same CPU model on diffrent host. CPUID[14] is

[Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console

HTIF (Host Target Interface) provides console emulation for QEMU. HTIF allows identical copies of BBL (Berkeley Boot Loader) and linux to run on both Spike and QEMU. BBL provides HTIF console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The HTIF interface

[Qemu-devel] [PATCH v5 07/23] RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions. Signed-off-by: Michael Clark --- fpu/softfloat-specialize.h | 7 +- target/riscv/fpu_helper.c | 375 + 2 files changed, 379 insertions(+), 3 deletions(-) create mode 100644

[Qemu-devel] [PATCH v5 14/23] SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer and interprocessor interrupts based on SiFive's CLINT specification. Signed-off-by: Michael Clark --- hw/riscv/sifive_clint.c | 312

[Qemu-devel] [PATCH v5 18/23] SiFive RISC-V UART Device

QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in

Re: [Qemu-devel] [PATCH v5 00/23] RISC-V QEMU Port Submission

To paraphrase; the case we are failing on is a corner case, where a register containing a double is used as input to a single precision op. It won't happen in correct code. On Thu, Feb 8, 2018 at 2:55 PM, Michael Clark wrote: > We are now passing all but one of the set of tests

[Qemu-devel] [PULL 13/16] block: Move NVMe constants to a separate header

Signed-off-by: Fam Zheng Reviewed-by: Stefan Hajnoczi Message-Id: <20180116060901.17413-8-f...@redhat.com> Signed-off-by: Fam Zheng --- block/nvme.c | 7 +- hw/block/nvme.h | 698

Re: [Qemu-devel] [PATCH v3] docs: Add docs/devel/testing.rst

On Wed, 02/07 15:31, Paolo Bonzini wrote: > On 01/02/2018 03:20, Fam Zheng wrote: > > To make our efforts on QEMU testing easier to consume by contributors, > > let's add a document. For example, Patchew reports build errors on > > patches that should be relatively easy to reproduce with a few

[Qemu-devel] [PULL 12/16] qemu-img: Map bench buffer

Signed-off-by: Fam Zheng Reviewed-by: Stefan Hajnoczi Message-Id: <20180116060901.17413-7-f...@redhat.com> Signed-off-by: Fam Zheng --- qemu-img.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/qemu-img.c

[Qemu-devel] [PATCH v5 16/23] RISC-V Spike Machines

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V Instruction Set Simulator. The following machines are implemented: - 'spike_v1.9'; HTIF console, config-string, Privileged ISA Version 1.9.1 - 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10 Signed-off-by:

[Qemu-devel] [PATCH v5 10/23] RISC-V Physical Memory Protection

Implements the physical memory protection extension as specified in Privileged ISA Version 1.10. PMP (Physical Memory Protection) is as-of-yet unused and needs testing. The SiFive verification team have PMP test cases that will be run. Nothing currently depends on PMP support. It would be

[Qemu-devel] [PATCH v5 04/23] RISC-V Disassembler

The RISC-V disassembler has no dependencies outside of the 'disas' directory so it can be applied independently. The majority of the disassembler is machine-generated from instruction set metadata: - https://github.com/michaeljclark/riscv-meta Expected checkpatch errors for consistency and

Re: [Qemu-devel] [PATCH v1] Implement support for IEEE 754-201x minimumNumber/maximumNumber

I've included this patch in the RISC-V patch series just submitted. The change is enclosed within a simple conditional so there is no risk of affecting any other ports. There was one line whitespace fix to the pre-existing code however it fell nicely within the diff hunk so I included the fix.

[Qemu-devel] [PULL 00/16] Docker and block patches

The following changes since commit 7b213bb4755dc99e447c19c532768ef5105b9771: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2018-02-07 20:40:36 +) are available in the Git repository at: git://github.com/famz/qemu.git tags/staging-pull-request for you

[Qemu-devel] [PULL 02/16] test-coroutine: add simple CoMutex test

From: Paolo Bonzini In preparation for adding a similar test using QemuLockable, add a very simple testcase that has two interleaved calls to lock and unlock. Reviewed-by: Stefan Hajnoczi Signed-off-by: Paolo Bonzini Message-Id:

[Qemu-devel] [PULL 04/16] coroutine-lock: convert CoQueue to use QemuLockable

From: Paolo Bonzini There are cases in which a queued coroutine must be restarted from non-coroutine context (with qemu_co_enter_next). In this cases, qemu_co_enter_next also needs to be thread-safe, but it cannot use a CoMutex and so cannot qemu_co_queue_wait. Use

  1   2   3   4   5   >