Re: [Qemu-devel] [PULL v2 00/20] Miscellaneous patches for 2018-02-07

2018-02-08 5:16 GMT+00:00 Markus Armbruster : > The following changes since commit 20e0d439a6ded635ec89f6135c08cd5541c68962: > > Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20180204' into > staging (2018-02-06 14:21:41 +) > > are available in the git

[Qemu-devel] [PATCH] misc: fix spelling

s/pupulate/populate Signed-off-by: Marc-André Lureau --- util/qemu-coroutine-lock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/qemu-coroutine-lock.c b/util/qemu-coroutine-lock.c index 846ff9167f..3d0152ebec 100644 ---

Re: [Qemu-devel] [PATCH] libvhost-user: Fix resource leak

On 01/18/2018 04:41 PM, Yongji Xie wrote: Free the mmaped memory when we need to mmap new memory space on vu_set_mem_table_exec() and vu_set_log_base_exec() to avoid memory leak. Also close the corresponding fd after mmap() on vu_set_log_base_exec() to avoid fd leak. Signed-off-by: Yongji

[Qemu-devel] [PATCH v11 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence

This series is expected to be taken by Paolo (he plan to fix few things). It includes the last versions of both series: - SDHCI: clean v1/v2 Specs (part 2) - SDHCI: add tuning sequence for UHS-I cards (part 3) Since v10: - rebased - add Paolo's R-b in patch 2 - rename patch 11 subject (Alistair)

[Qemu-devel] [PATCH v11 02/30] sdhci: add qtest to check the SD capabilities register

The PCI model is tested with the pc/x86_64 machine, the SysBus model with the smdkc210/arm machine. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini --- tests/sdhci-test.c | 139 +

[Qemu-devel] [PATCH v11 03/30] sdhci: add check_capab_readonly() qtest

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Stefan Hajnoczi --- tests/sdhci-test.c | 24 1 file changed, 24 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index 1105e07093..e961f2b997 100644 ---

[Qemu-devel] [PATCH v11 01/30] sdhci: use error_propagate(local_err) in realize()

avoid the "errp && *errp" pattern (not recommended in "qapi/error.h" comments). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git

[Qemu-devel] [PATCH v11 21/30] sdhci: implement UHS-I voltage switch

[based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/sd/sd.h| 16 include/hw/sd/sdhci.h |

[Qemu-devel] [PATCH v11 28/30] sdhci: check Spec v3 capabilities qtest

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- tests/sdhci-test.c | 12 tests/Makefile.include | 1 + 2 files changed, 13 insertions(+) diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c index

[Qemu-devel] [PATCH 1/3] block: add BlockBackend->in_flight counter

BlockBackend currently relies on BlockDriverState->in_flight to track requests for blk_drain(). There is a corner case where BlockDriverState->in_flight cannot be used though: blk->root can be NULL when there is no medium. This results in a segfault when the NULL pointer is dereferenced.

[Qemu-devel] [PATCH 0/3] block: fix blk_aio_*() segfault when blk->root == NULL

Using bdrv_inc_in_flight(blk_bs(blk)) doesn't work since BlockBackend->root may be NULL. This patch series solves the issue by adding an BlockBackend->in_flight counter so requests can be tracked even when there is no BlockDriverState. This should fix the IDE and virtio-blk segfaults that have

[Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c793250186..f976969011 100644 --- a/target/arm/cpu.h +++

[Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16

I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 29 + 1 file changed, 21 insertions(+), 8 deletions(-) diff --git

[Qemu-devel] [PATCH 1/2] hw/arm/aspeed: directly map the serial device to the system address space

Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/aspeed_soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index c83b7e207b..a786750e14 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -257,7 +257,7 @@

[Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée --- v2 remove superfluous helpers --- target/arm/helper-a64.c| 13 + target/arm/helper-a64.h| 1 + target/arm/translate-a64.c | 5 + 3 files changed, 19 insertions(+) diff --git a/target/arm/helper-a64.c

[Qemu-devel] [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16

As these operations doesn't use the fpstatus pointer we can be smarter about allocating it. The negh can also be done with a bitwise xor rather than calling a helper. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 14 ++ 1 file changed, 14

[Qemu-devel] [PATCH 3/4] 9pfs: stat_to_qid: use device as input to qid.path

From: Antonios Motakis To support multiple devices on the 9p share, and avoid qid path collisions we take the device id as input to generate a unique QID path. The lowest 48 bits of the path will be set equal to the file inode, and the top bits will be uniquely

Re: [Qemu-devel] [PATCH 1/2] hw/arm/aspeed: directly map the serial device to the system address space

On 02/08/2018 02:30 PM, Peter Maydell wrote: > On 8 February 2018 at 17:22, Philippe Mathieu-Daudé wrote: >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/arm/aspeed_soc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git

Re: [Qemu-devel] [PATCH 3/3] build-sys: enable sanitizers by default with --enable-debug

Hi On Thu, Feb 8, 2018 at 6:46 PM, Paolo Bonzini wrote: > On 08/02/2018 17:23, Marc-André Lureau wrote: >> The original commit 247724cb302af5d70c8853154b640dfabf2bbb56 was meant >> to enable sanitizers by default when --enable-debug, but failed >> because of a gcc static

Re: [Qemu-devel] [PATCH 1/1] nbd: increase maximum size of the PWRITE_ZERO request

On 02/08/2018 09:28 AM, Edgar Kaziakhmedov wrote: We've got a potential problem.  Unless you have out-of-band communication of the maximum NBD_CMD_WRITE_ZEROES sizing (or if the NBD protocol is enhanced to advertise that as an additional piece of block size information during NBD_OPT_GO),

Re: [Qemu-devel] [PULL 00/16] Docker and block patches

On 8 February 2018 at 02:19, Fam Zheng wrote: > The following changes since commit 7b213bb4755dc99e447c19c532768ef5105b9771: > > Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into > staging (2018-02-07 20:40:36 +) > > are available in the Git repository

[Qemu-devel] [PATCH 2/3] build-sys: check static linking of UBSAN

Signed-off-by: Marc-André Lureau --- configure | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 41d8a2666c..beb0de6a77 100755 --- a/configure +++ b/configure @@ -5247,7 +5247,15 @@ fi

Re: [Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console

On 02/07/2018 05:28 PM, Michael Clark wrote: > +++ b/hw/riscv/riscv_elf.c > @@ -0,0 +1,244 @@ > +/* > + * elf.c - A simple package for manipulating symbol tables in elf binaries. > + * > + * Taken from > + * https://www.cs.cmu.edu/afs/cs.cmu.edu/academic/class/15213-f03/www/ > + * ftrace/elf.c > +

[Qemu-devel] [PATCH v2] S390: Expose s390-specific CPU info

Presently s390x is the only architecture not exposing specific CPU information via QMP query-cpus. Upstream discussion has shown that it could make sense to report the architecture specific CPU state, e.g. to detect that a CPU has been stopped. With this change the output of query-cpus will look

Re: [Qemu-devel] [PATCH] S390: Expose s390-specific CPU info

On Thu, 8 Feb 2018 16:52:28 +0100 Viktor Mihajlovski wrote: > diff --git a/qapi-schema.json b/qapi-schema.json > index 12c7dc8..0b36860 100644 > --- a/qapi-schema.json > +++ b/qapi-schema.json > @@ -607,7 +607,27 @@ > ## > { 'struct': 'CpuInfo2', >'data':

[Qemu-devel] [PATCH v11 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet

checking Xilinx datasheet "UG1085" (v1.7) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/xlnx-zynqmp.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git

[Qemu-devel] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode

As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Bennée --- target/arm/helper.c| 4 ++--

Re: [Qemu-devel] [PATCH v5 09/14] pci: Use pci_config_size in pci_data_* accessors

On 7 February 2018 at 04:24, Andrey Smirnov wrote: > Use pci_config_size (as opposed to PCI_CONFIG_SPACE_SIZE) in > pci_data_read() and pci_data_write(), so this function would work for > both classic PCI and PCIe use-cases. > > Cc: Peter Maydell

[Qemu-devel] [PATCH v2 03/32] target/arm/cpu64: allow fp16 to be disabled

While for CONFIG_USER_ONLY it is policy for the "cpu" to be the most capable is can be this does cause problems. For example legacy RISU runs would fail as there are a bunch of implemented instructions which would have caused failures that now trigger actual calculations. Signed-off-by: Alex

Re: [Qemu-devel] [PATCH] S390: Expose s390-specific CPU info

On Thu, 8 Feb 2018 18:02:07 +0100 Viktor Mihajlovski wrote: > On 08.02.2018 17:22, Luiz Capitulino wrote: > > On Thu, 8 Feb 2018 16:52:28 +0100 > > Viktor Mihajlovski wrote: > > > >> diff --git a/qapi-schema.json b/qapi-schema.json >

[Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16

This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 22 target/arm/helper-a64.h| 2 + target/arm/translate-a64.c | 136

[Qemu-devel] [PATCH 4/4] 9pfs: stat_to_qid: implement slow path

From: Antonios Motakis stat_to_qid attempts via qid_path_prefixmap to map unique files (which are identified by 64bt inode nr and 32 bit device id) to a 64 QID path value. However this implementation makes some assumptions about inode number generation on the host.

Re: [Qemu-devel] [PULL v2 00/20] Miscellaneous patches for 2018-02-07

On 02/08/2018 10:22 AM, Peter Maydell wrote: 2018-02-08 5:16 GMT+00:00 Markus Armbruster : The following changes since commit 20e0d439a6ded635ec89f6135c08cd5541c68962: Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20180204' into staging (2018-02-06 14:21:41

Re: [Qemu-devel] [RFC PATCH 3/5] vfio/quirks: Automatic ioeventfd enabling for NVIDIA BAR0 quirks

On Thu, 8 Feb 2018 12:10:02 +0100 Auger Eric wrote: > Hi Alex, > > On 07/02/18 01:26, Alex Williamson wrote: > > Record data writes that come through the NVIDIA BAR0 quirk, if we get > > enough in a row that we're only passing through, automatically enable > > an

[Qemu-devel] [PATCH 3/3] build-sys: enable sanitizers by default with --enable-debug

The original commit 247724cb302af5d70c8853154b640dfabf2bbb56 was meant to enable sanitizers by default when --enable-debug, but failed because of a gcc static linking bug. Try to enable it back now that there is a stronger check. Signed-off-by: Marc-André Lureau ---

[Qemu-devel] [PATCH v2] qmp: add query-cpus-fast

The query-cpus command has an extremely serious side effect: it always interrupts all running vCPUs so that they can run ioctl calls. This can cause a huge performance degradation for some workloads. And most of the information retrieved by the ioctl calls are not even used by query-cpus. This

[Qemu-devel] [PATCH v11 10/30] sdhci: check the Spec v1 capabilities correctness

Incorrect value will throw an error. Note than Spec v2 is supported by default. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 21 ++- hw/sd/sdhci.c | 97

[Qemu-devel] [PATCH v11 08/30] sdhci: use a numeric value for the default CAPAB register

using many #defines is not portable when scaling to different HCI. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci.c | 74 +-- 1 file changed, 16

[Qemu-devel] [PULL v2 00/20] tcg generic vectors

: Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into staging (2018-02-08 10:16:59 +) are available in the Git repository at: git://github.com/rth7680/qemu.git tags/pull-tcg-20180208 for you to fetch changes up to 14e4c1e2355473ccb2939afc69ac8f25de103b92: tcg/aa

[Qemu-devel] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)

This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée -- v1 - dropped the

Re: [Qemu-devel] [PATCH 2/3] build-sys: check static linking of UBSAN

On 02/08/2018 10:23 AM, Marc-André Lureau wrote: Signed-off-by: Marc-André Lureau --- configure | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 41d8a2666c..beb0de6a77 100755 --- a/configure +++ b/configure

[Qemu-devel] [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

I only needed to do a little light re-factoring to support the half-precision helpers. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 80 +++--- 1 file changed, 54 insertions(+), 26 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions

Hi, This series failed docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180208173157.24705-1-alex.ben...@linaro.org Subject: [Qemu-devel] [PATCH v2 00/32] Add

[Qemu-devel] [PATCH 2/4] 9pfs: check for file device to avoid QID path collisions

From: Antonios Motakis The QID path should uniquely identify a file. However, the inode of a file is currently used as the QID path, which on its own only uniquely identifies wiles within a device. Here we track the device hosting the 9pfs share, in order to prevent

[Qemu-devel] [Bug 1343827] Re: block.c: multiwrite_merge() truncates overlapping requests

Triaging old bug tickets... has Stefan's fix be included? Could we close this ticket nowadays? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [Qemu-devel] [PATCH 1/1] nbd: increase maximum size of the PWRITE_ZERO request

On 02/08/2018 06:55 PM, Eric Blake wrote: On 02/08/2018 09:28 AM, Edgar Kaziakhmedov wrote: We've got a potential problem.  Unless you have out-of-band communication of the maximum NBD_CMD_WRITE_ZEROES sizing (or if the NBD protocol is enhanced to advertise that as an additional piece of

[Qemu-devel] [PATCH v11 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet

checking Xilinx datasheet "UG585" (v1.12.1) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/xilinx_zynq.c | 53 tests/sdhci-test.c | 5 + 2 files changed, 34

[Qemu-devel] [PATCH v11 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/arm/bcm2835_peripherals.c | 21 + 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c

Re: [Qemu-devel] [PATCH v5 00/14] Initial i.MX7 support

On Thu, Feb 8, 2018 at 5:49 AM, Peter Maydell wrote: > On 7 February 2018 at 04:24, Andrey Smirnov wrote: >> Hi everyone, >> >> This v5 of the patch series containing the work that I've done in >> order to enable support for i.MX7 emulation in

[Qemu-devel] [PATCH v11 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB

following the datasheet. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/arm/bcm2835_peripherals.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/bcm2835_peripherals.c

[Qemu-devel] [PATCH 3/3] Revert "IDE: Do not flush empty CDROM drives"

This reverts commit 4da97120d51a4383aa96d741a2b837f8c4bbcd0b. blk_aio_flush() now handles the blk->root == NULL case, so we no longer need this workaround. Cc: John Snow Signed-off-by: Stefan Hajnoczi --- hw/ide/core.c | 10 +- 1 file changed, 1

[Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16

This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée ---

[Qemu-devel] [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16

Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final

[Qemu-devel] [Bug 1747393] Re: nvme is missing support for NVME_ADM_CMD_ASYNC_EV_REQ

** Description changed: NVME_ADM_CMD_ASYNC_EV_REQ is required by specification but apparently we will be responded by error when this command is used. + + The Asynchronous Event Request is a mandatory opcode required by + specification (Figure 40, Section 5 in NVMe 1.2; Figure 41, Section 5

Re: [Qemu-devel] [PATCH v5 09/14] pci: Use pci_config_size in pci_data_* accessors

On 8 February 2018 at 17:43, Andrey Smirnov wrote: > My only justification for this change was suggestion from Marcel to > use pci_data_* functions, instead of calling pci_host_config_*_common > explicitly in designware.c introduced in next patch in the series. My > v4

[Qemu-devel] [PATCH] lpc: drop pcie host dependency

Doesn't look like that header is used. Signed-off-by: Michael S. Tsirkin --- hw/isa/lpc_ich9.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index adcf077..e692b9f 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -39,7 +39,6

Re: [Qemu-devel] [PATCH] block: unify blocksize types

CC qemu-block On 02/08/2018 08:28 AM, Piotr Sarna wrote: > BlockSizes structure used in block size probing has uint32_t types > for logical and physical sizes. These fields are wrongfully assigned > to uint16_t in BlockConf, which results, among other errors, > in assigning 0 instead of 65536

[Qemu-devel] [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16

Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 587d072d27..fa21299061 100644 --- a/target/arm/translate-a64.c +++

Re: [Qemu-devel] [RFC PATCH 5/5] vfio/quirks: Enable ioeventfd quirks to be handled by vfio directly

On Thu, 8 Feb 2018 12:42:15 +0100 Auger Eric wrote: > Hi Alex, > On 07/02/18 01:26, Alex Williamson wrote: > > With vfio ioeventfd support, we can program vfio-pci to perform a > > specified BAR write when an eventfd is triggered. This allows the > > KVM ioeventfd to be

[Qemu-devel] [Bug 1331334] Re: driftfix=none and migration on Win7 guest causes time to go 10 times as fast

Triaging old bug tickets... can you still reproduce this issue with the latest version of QEMU? Or could we close this ticket nowadays? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Qemu-devel] [Bug 1225187] Re: qemu hangs in windows 7 host with -serial pipe:windbg

Triaging old bug tickets... can you still reproduce this issue with the latest version of QEMU? Or could we close this ticket nowadays? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence)

[based on a patch from Alistair Francis from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 10 ++ include/hw/sd/sdhci.h | 1 +

[Qemu-devel] [PATCH v2 13/32] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16

Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 34 ++ target/arm/helper-a64.h| 2 ++ target/arm/translate-a64.c | 6 ++ 3 files changed, 42 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

Re: [Qemu-devel] [PATCH v5 09/14] pci: Use pci_config_size in pci_data_* accessors

On Thu, Feb 8, 2018 at 9:34 AM, Michael S. Tsirkin wrote: > On Thu, Feb 08, 2018 at 05:20:53PM +, Peter Maydell wrote: >> On 7 February 2018 at 04:24, Andrey Smirnov wrote: >> > Use pci_config_size (as opposed to PCI_CONFIG_SPACE_SIZE) in >> >

Re: [Qemu-devel] [PATCH v5 10/14] pci: Add support for Designware IP block

On Tue, Feb 06, 2018 at 08:24:34PM -0800, Andrey Smirnov wrote: > Add code needed to get a functional PCI subsytem when using in > conjunction with upstream Linux guest (4.13+). Tested to work against > "e1000e" (network adapter, using MSI interrupts) as well as > "usb-ehci" (USB controller, using

[Qemu-devel] [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm

Only one half-precision instruction has been added to this group. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 48 -- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] target-i386: adds PV_DEDICATED hint CPUID feature bit

On Thu, Feb 08, 2018 at 05:44:20PM +0800, Wanpeng Li wrote: > From: Wanpeng Li > > Add PV_DEDICATED hint cpuid feature bit. > [...] > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index d70954b..cf48931 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c >

[Qemu-devel] [Bug 1211943] Re: #GP and aligned move instruction

Triaging old bug tickets... can you still reproduce this issue with the latest version of QEMU? Or could we close this ticket nowadays? ** Changed in: qemu Status: New => Incomplete -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to

[Qemu-devel] [PATCH v2 14/32] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 208 + 1 file changed, 133 insertions(+), 75 deletions(-) diff --git

Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions

Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20180208173157.24705-1-alex.ben...@linaro.org Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions === TEST SCRIPT BEGIN === #!/bin/bash BASE=base

[Qemu-devel] [PULL 00/26] virtio, vhost, pci, pc: features, fixes and cleanups

The following changes since commit 008a51bbb343972dd8cf09126da8c3b87f4e1c96: Merge remote-tracking branch 'remotes/famz/tags/staging-pull-request' into staging (2018-02-08 14:31:51 +) are available in the git repository at: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git

[Qemu-devel] [PULL 01/26] Revert "vhost: add traces for memory listeners"

This reverts commit 0750b060216de69ed1f14bc08181bf4ad27fc622. Follow up patches are reworking the memory listeners, the new mechanism will add its own set of traces. Signed-off-by: Michael S. Tsirkin --- hw/virtio/vhost.c | 7 --- hw/virtio/trace-events | 6 -- 2

Re: [Qemu-devel] [PATCH v5 11/23] RISC-V Linux User Emulation

On 02/07/2018 05:28 PM, Michael Clark wrote: > +/* not RISC-V exception codes - this is for qemu user-mode */ > +#define QEMU_USER_EXCP_FAULT 0xd Any reason to define this instead of using RISCV_EXCP_LOAD_ADDR_MIS/ACCESS_FAULT? Otherwise this looks fine. Reviewed-by: Richard

Re: [Qemu-devel] [PATCH v6 18/23] sev: emit the SEV_MEASUREMENT event

On Thu, Feb 08, 2018 at 10:17:28AM -0600, Brijesh Singh wrote: > > Anyway, the main issue is event emitted before "qmp_capabilities" are > dropped silently , see [1] . In our case, the measurement event is emitted > during the machine creation time, libvirt was still waiting to reconnect > the

Re: [Qemu-devel] [PATCH v4 3/3] qemu: add linkspeed and duplex settings to virtio-net

On Fri, Jan 05, 2018 at 05:44:55PM -0500, Jason Baron wrote: > Although linkspeed and duplex can be set in a linux guest via 'ethtool -s', > this requires custom ethtool commands for virtio-net by default. > > Introduce a new feature flag, VIRTIO_NET_F_SPEED_DUPLEX, which allows > the hypervisor

Re: [Qemu-devel] [PATCH] libvhost-user: Support across-memory-boundary access

On 01/18/2018 05:04 PM, Yongji Xie wrote: The sg list/indirect descriptor table may be contigious in GPA but not in HVA address space. But libvhost-user wasn't aware of that. This would cause out-of-bounds access. Even a malicious guest could use it to get information from the vhost-user

[Qemu-devel] [PATCH v11 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus)

Incorrect value will throw an error. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 14 +++--- hw/sd/sdhci.c | 19 +++ 2 files changed, 22 insertions(+), 11

[Qemu-devel] [PATCH v11 12/30] sdhci: Fix 64-bit ADMA2

From: Sai Pavan Boddu The 64-bit ADMA address is not converted to the cpu endianes correctly. This patch fixes the issue and uses a valid mask for the attribute data. Signed-off-by: Sai Pavan Boddu [AF: Re-write commit message] Reviewed-by: Alistair

[Qemu-devel] [PATCH v11 09/30] sdhci: simplify sdhci_get_fifolen()

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/sd/sdhci-internal.h | 4 +++- hw/sd/sdhci.c | 20 +--- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/hw/sd/sdhci-internal.h

[Qemu-devel] [PULL v2 01/20] tcg: Allow multiple word entries into the constant pool

This will be required for storing vector constants. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg-pool.inc.c | 113

[Qemu-devel] [PATCH v11 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3

Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/arm/fsl-imx6.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index b0d4088290..1f4607f206 100644 --- a/hw/arm/fsl-imx6.c +++

Re: [Qemu-devel] [PATCH] S390: Expose s390-specific CPU info

On 08.02.2018 17:22, Luiz Capitulino wrote: > On Thu, 8 Feb 2018 16:52:28 +0100 > Viktor Mihajlovski wrote: > >> diff --git a/qapi-schema.json b/qapi-schema.json >> index 12c7dc8..0b36860 100644 >> --- a/qapi-schema.json >> +++ b/qapi-schema.json >> @@ -607,7 +607,27

Re: [Qemu-devel] [PATCH v5 2/3] xlnx-zynqmp-rtc: Add basic time support

On Thu, Feb 8, 2018 at 7:42 AM, Peter Maydell wrote: > On 26 January 2018 at 01:09, Alistair Francis > wrote: >> On Thu, Jan 25, 2018 at 3:36 AM, Peter Maydell >> wrote: >>> I'm still not sure about having the

Re: [Qemu-devel] [PATCH v2] S390: Expose s390-specific CPU info

On 08.02.2018 17:43, Viktor Mihajlovski wrote: > Presently s390x is the only architecture not exposing specific > CPU information via QMP query-cpus. Upstream discussion has shown > that it could make sense to report the architecture specific CPU > state, e.g. to detect that a CPU has been

[Qemu-devel] [PATCH 0/2] aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

The diffstat prooves it :) Philippe Mathieu-Daudé (2): hw/arm/aspeed: directly map the serial device to the system address space hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io include/hw/arm/aspeed_soc.h | 1 - hw/arm/aspeed_soc.c | 34

[Qemu-devel] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags

Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Bennée

[Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16

It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final

[Qemu-devel] [PATCH v2 24/32] arm/translate-a64: add FP16 FRECPE

Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 8 1 file changed, 8 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index

[Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half

This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use existing helpers to achieve this. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 72 ++ 1 file changed, 72 insertions(+) diff --git

[Qemu-devel] [PATCH 1/4] 9pfs: V9fsQID: set type of version and path to unsigned

From: Antonios Motakis There is no need for signedness on these QID fields for 9p. Signed-off-by: Antonios Motakis --- fsdev/9p-marshal.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fsdev/9p-marshal.h

Re: [Qemu-devel] [PATCH 2/2] hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io

On 02/08/2018 06:22 PM, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé This looks like a good idea. (Have you actually tried it ? just asking) Reviewed-by: Cédric Le Goater Thanks, C. > --- > include/hw/arm/aspeed_soc.h | 1 - >

[Qemu-devel] [PATCH 1/3] build-sys: remove useless extra*flags variables

Only EXTRA_LDFLAGS seems to be used during configure Xen checks. Signed-off-by: Marc-André Lureau --- configure | 6 -- 1 file changed, 6 deletions(-) diff --git a/configure b/configure index 831ebf248f..41d8a2666c 100755 --- a/configure +++ b/configure @@

Re: [Qemu-devel] [PATCH v5 13/23] RISC-V HART Array

On 02/07/2018 05:28 PM, Michael Clark wrote: > Holds the state of a heterogenous array of RISC-V hardware threads. > > Signed-off-by: Michael Clark > --- > hw/riscv/riscv_hart.c | 95 > +++ > include/hw/riscv/riscv_hart.h | 45

[Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register

As per the Spec v3.00 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- include/hw/sd/sdhci.h | 2 +- hw/sd/sdhci.c | 12 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git

Re: [Qemu-devel] [PATCH] misc: fix spelling

On 8 February 2018 at 16:24, Marc-André Lureau wrote: > s/pupulate/populate > > Signed-off-by: Marc-André Lureau > --- > util/qemu-coroutine-lock.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

[Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16

Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 49 ++ target/arm/helper-a64.h| 5 + target/arm/translate-a64.c | 15 ++ 3 files changed, 69 insertions(+) diff --git a/target/arm/helper-a64.c

[Qemu-devel] [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit

Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7c922d79b..c793250186 100644 ---

Re: [Qemu-devel] [PATCH v5 09/14] pci: Use pci_config_size in pci_data_* accessors

On Thu, Feb 08, 2018 at 05:20:53PM +, Peter Maydell wrote: > On 7 February 2018 at 04:24, Andrey Smirnov wrote: > > Use pci_config_size (as opposed to PCI_CONFIG_SPACE_SIZE) in > > pci_data_read() and pci_data_write(), so this function would work for > > both classic

[Qemu-devel] [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16

We go with the localised helper. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 29 + target/arm/helper-a64.h| 1 + target/arm/translate-a64.c | 4 3 files changed, 34 insertions(+) diff --git a/target/arm/helper-a64.c

[Qemu-devel] [PATCH v2 19/32] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16

This covers all the floating point convert operations. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c| 32 + target/arm/helper-a64.h| 2 ++ target/arm/translate-a64.c | 85 +- 3 files changed,

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